Theory of composable latency-insensitive refinements

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 36-37).Simulation of a synchronous system on a hardware platform, for example an FPGA, can be performed using a hardware prototype of the system. But the prototype may not meet the resource and timing constraints of that platform. One way to meet the constraints is to partition the prototype hierarchically into modules, and to refine the individual modules while preserving the overall behavior of the system. In this thesis we formalize the notion of a refinement that preserves the behavior of the original modules - we call such refinements latency-insensitive refinements. We show that if these latency-insensitive refinements of the modules obey certain conditions, then these refinements can be composed together hierarchically in order to obtain the latency-insensitive refinement of the original system. We call the latency-insensitive refinements that obey these conditions as composable latency-insensitive refinements. We also give a procedure to automatically transform a module to a latency-insensitive refinement while obeying the conditions that enable it to be composed hierarchically. The transformation serves as a starting point for making further refinements and optimizations, and thus, gives a methodology to design hardware simulators for synchronous systems.by Muralidaran Vijayaraghavan.S.M

ReSim, a Trace-Driven, Reconfigurable ILP Processor Simulator

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. In this paper we propose ReSim, a parameterizable ILP processor simulation acceleration engine based on reconfigurable hardware. We describe ReSim’s trace-driven microarchitecture that allows us to simulate the operation of a complex ILP processor in a cycle serial fashion, aiming to simplify implementation complexity and to boost operating frequency. Being trace driven, ReSim can simulate timing in an almost ISA independent fashion, and supports all SimpleScalar ISAs, i.e. PISA, Alpha, etc. We implemented ReSim for the latest Xilinx devices. In our experiments with a 4-way superscalar processor ReSim achieves a simulation throughput of up to 28MIPS, and offers more than a factor of 5x improvement over the best reported ILP processor hardware simulators

Hybrid prototyping of multicore embedded systems

Multicore platforms are becoming increasingly pervasive in modern embedded systems. System level modeling techniques have enabled creation of fast software models of multicore platforms, commonly known as Virtual Prototypes, for early functional validation of embedded software, before the hardware is available. On the other hand, for accurate performance validation, the complete multicore platform can be implemented as a physical prototype on FPGA. Both virtual platforms and FPGA prototypes have their respective pros and cons. Virtual platforms have the advantage of high speed functional simulation and, typically, scale well with the number of cores. However, the accuracy of performance estimation is sacrificed. FPGA prototypes provide cycle-accurate performance estimation, because the software executes directly on an FPGA implementation of the target cores. However, it takes a significant amount of time to design, implement and test the inter-core communication architecture on the FPGA. In this thesis we propose to design a novel system-level modeling framework, called Hybrid Prototyping. Our goal is to provide the benefits of both virtual platforms and FPGA prototypes. It aims to provide early, fast, and scalable models, similar to virtual platforms, along with the cycle-accuracy of FPGA prototypes. Using hybrid prototyping, embedded software designers will be able to create concurrent applications and accurately analyze the performance implication of their optimizations before the chip is delivered. At the same time, multicore architects will be able to modify the platform model without having to do full system prototyping. Therefore, hybrid prototyping will enable early and reliable multicore embedded system design, resulting in huge productivity gains for both embedded software designers and multicore chip architects

Interacção remota com circuitos implementados em FPGA

Mestrado em Engenharia Electrónica e TelecomunicaçõesCom crescente utilização nos últimos anos de dispositivos como as FPGAs, a construção de módulos reutilizáveis tornou-se importante para a implementação de sistemas cada vez mais complexos. Este tipo de sistemas frequentemente necessita comunicação remota para diversos fins, como por exemplo para controlo remoto, alteração de parâmetros, verificação de estados, entre outros. Nesta tese foi assim desenvolvido um bloco reutilizável que forneça aos sistemas baseados em FPGA a capacidade de comunicarem sem fios. Dentro dos sistemas implementados em FPGA, foi analisada a aplicabilidade na prática de modelos avançados de máquinas de estados finitos, para a implementação em hardware de algoritmos de controlo modulares, hierárquicos, recursivos e paralelos. Para isso, foi implementado um componente reutilizável, denominado buffer de prioridade, que é descrito em detalhe e é sintetizado a partir de uma especificação modular, hierárquica, recursiva e paralela. Nesta dissertação também é descrito um sistema para controlo automático de um parque de estacionamento. Este sistema composto pelo controlo central e pelo controlo de cada carro são inicialmente ligados directamente, dentro da mesma FPGA, para efeitos de simulação. Para a gestão dos lugares é aplicado o buffer de prioridade construído anteriormente. Por fim, é demonstrado um sistema com controlo remoto, através da implementação da interface sem fios desenvolvida entre o controlo central e o controlo dos carros. O protótipo do sistema completo foi projectado, implementado em FPGA, avaliado e testado com êxito. Os resultados pertinentes podem ser avaliados através de uma simulação visual apresentada num monitor VGA, evitando assim a necessidade de um ambiente físico dispendioso. Alguns resultados desta tese serão publicados num artigo [1] aceite para apresentação numa conferência internacional

Cycle-accurate multicore performance models on FPGAs

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 159-165).The goal of this project is to improve computer architecture by accelerating cycle-accurate performance modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with realistic On-Chip Networks.by Michael Pellauer.Ph.D