Closed Form Expressions for Delay to Ramp Inputs for On-Chip VLSI RC Interconnect

In high speed digital integrated circuits, interconnects delay can be significant and should be included for accurate analysis. Delay analysis for interconnect has been done widely by using moments of the impulse response, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees it is demonstrated that the inverse gamma function provides a provably stable approximation. We used the PERI [13] (Probability distribution function Extension for Ramp Inputs) technique that extends delay metrics for ramp inputs to the more general and realistic non-step inputs. The accuracy of our model is justified with the results compared with that of SPICE simulations. Keywords¾ Moment Matching, On-Chip Interconnect, Probability Distribution function, Cumulative Distribution function, Delay calculation, Slew Calculation, Beta Distribution, VLSI

Simulation Study on Different Logic Families of NOT Gate Transistor Level Circuits Implemented Using Nano-MOSFETs

In this paper, a simulation study has been done on logic NOT transistor circuits with four different logic families, namely: (i) nano-CMOS NOT gate, (ii) nano-MOSFET loaded ntype nano-MOSFET NOT gate, (iii) resistive loaded nanoMOSFET NOT gate, and (iv) pseudo nano-MOSFET NOT gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on the type of logic families. Simulated timing diagrams for input and output waveforms showed correct logical NOT gate operations for all four logic families. Additionally, the voltage transfer characteristic (VTC) curves have been plotted for all four logic families. From the VTC plots, logic swing (VLS), transition width (VTW), high noise margin (VNMH), low noise margin (VNML), high noise sensitivity (VNSH), low noise sensitivity (VNSL), high noise immunity (VNIH) and low noise immunity (VNIL) have been obtained. Analysis on these values indicated that all the four logic NOT gate families which consist of nano-transistors meet the NOT gate operation conditions. Drain current, intrinsic delay and dynamic power are discussed as the effects of down scaling. In conclusion, NOT gates made of nano-MOSFETs with nanometer dimensions are able to perform correct logical operations in the same way as NOT gates made up of conventional bulk MOSFETs as proven by timing diagrams and VTC plots

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

With the advent of many-core chips that place substantial demand on the NoC, photonics has been investigated as a promising alternative to electrical NoCs. While numerous opto-electronic NoCs have been proposed, their evaluations tend to be based on fixed numbers for both photonic and electrical components, making it difficult to co-optimize. Through our own forays into opto-electronic NoC design, we observe that photonics and electronics are very much intertwined, reflecting a strong need for a NoC modeling tool that accurately models parameterized electronic and photonic components within a unified framework, capturing their interactions faithfully. In this paper, we present a tool, DSENT, for design space exploration of electrical and opto-electrical networks. We form a framework that constructs basic NoC building blocks from electrical and photonic technology parameters. To demonstrate potential use cases, we perform a network case study illustrating data-rate tradeoffs, a comparison with scaled electrical technology, and sensitivity to photonics parameters

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

In this thesis, we present a fast algorithm to construct a performance driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently several algorithms like Ptree, Stree, Sptree, and graph-RTBW have been published addressing the routing tree construction problem. But all these algorithms are slow and not scalable. Here we present an algorithm which is fast and scalable with problem size. The main idea of algorithm is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features to evaluate a routing tree, the size of stochastic search space is small which can be searched in very less time. The solutions for the components are either pre-generated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since, the solutions of the components can be constructed efficiently, we can construct and evaluate the whole routing tree efficiently for each specification. Experimental results show that, for trees of moderate size, our algorithm is at least several hundred times faster than the recently proposed algorithms, Sptree and graph-RTBW, with not much difference in delay and resource consumption

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered

Interconnect delay modeling under exponential input

Interconnect has become the dominating factor in determining the performance of VLSI deep submicron designs. With the rapid shrinking of feature size and development in the process technologies, it has been observed that the resistance per unit length of the interconnect continues to increase, capacitance per unit length remains roughly constant, and transistor or gate delay continues to decrease. This had led to the increasing dominance of interconnect delay over logic delay, and this trend is expected to continue. With this being the main bottleneck in realizing high speed circuits, complete understanding of the interconnect delay and thereby efficient and accurate delay circulation has assumed a greater significance in physical design, optimization and fast verification. In this thesis, a interconnect delay model under exponential input is presented. Because of its simple closed form expression, fast computation speed, and fidelity with respect to simulation, Elmore delay model remains popular. More accurate delay computation methods are typically central processing unit intensive and/or difficult to implement. To bridge this gap between accuracy and efficiency/simplicity, a new RC delay metric for interconnects which is as efficient as the Elmore metric, but more accurate, is proposed. However, there is no interconnect delay model considering exponential input waveform existing in the literature. The proposed Exponential Delay Metric uses exponential waveform as input and captures resistive shielding effects by modeling the downstream by a [pi]-model. An application of the delay model to perform interconnect optimization using wire sizing is also presented. Experimental results show that the proposed delay model is significantly more accurate than the existing interconnect delay models

Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime