Testing the bus guardian unit of the FTMP

Fault-tolerant multiprocessor (FTMP) operation is discussed. Fault-modeling in the bus guardian units (BGUs) is covered. Testing the BGU is discussed. A testing algorithm is proposed

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Diagnostic Applications for Micro-Synchrophasor Measurements

This report articulates and justifies the preliminary selection of diagnostic applications for data from micro-synchrophasors (µPMUs) in electric power distribution systems that will be further studied and developed within the scope of the three-year ARPA-e award titled Micro-synchrophasors for Distribution Systems

Fault propagation timing analysis to aid in the selection of sensors fro health management systems

Sensor data is processed to assess performance and health of complex systems. Proper sensor selection, placement, and implementation are critical to build an effective health management system. For complex systems in which the timely assessment of the health is desired to avoid expensive consequences of failure, sensor placement is vital. The ability to identify a critical failure early is completely dependent on sensor location within the fault propagation path. A strategy for assessing a sensor suite with respect to timely critical failure detection is presented in this thesis. To illustrate the strategy, Fault Propagation Timing Analysis (FPTA) will be performed on the Rocketdyne RS-68 rocket engine --Abstract, page iii

A Verified Information-Flow Architecture

SAFE is a clean-slate design for a highly secure computer system, with pervasive mechanisms for tracking and limiting information flows. At the lowest level, the SAFE hardware supports fine-grained programmable tags, with efficient and flexible propagation and combination of tags as instructions are executed. The operating system virtualizes these generic facilities to present an information-flow abstract machine that allows user programs to label sensitive data with rich confidentiality policies. We present a formal, machine-checked model of the key hardware and software mechanisms used to dynamically control information flow in SAFE and an end-to-end proof of noninterference for this model. We use a refinement proof methodology to propagate the noninterference property of the abstract machine down to the concrete machine level. We use an intermediate layer in the refinement chain that factors out the details of the information-flow control policy and devise a code generator for compiling such information-flow policies into low-level monitor code. Finally, we verify the correctness of this generator using a dedicated Hoare logic that abstracts from low-level machine instructions into a reusable set of verified structured code generators

A Systematic Aspect-Oriented Refactoring and Testing Strategy, and its Application to JHotDraw

Aspect oriented programming aims at achieving better modularization for a system's crosscutting concerns in order to improve its key quality attributes, such as evolvability and reusability. Consequently, the adoption of aspect-oriented techniques in existing (legacy) software systems is of interest to remediate software aging. The refactoring of existing systems to employ aspect-orientation will be considerably eased by a systematic approach that will ensure a safe and consistent migration. In this paper, we propose a refactoring and testing strategy that supports such an approach and consider issues of behavior conservation and (incremental) integration of the aspect-oriented solution with the original system. The strategy is applied to the JHotDraw open source project and illustrated on a group of selected concerns. Finally, we abstract from the case study and present a number of generic refactorings which contribute to an incremental aspect-oriented refactoring process and associate particular types of crosscutting concerns to the model and features of the employed aspect language. The contributions of this paper are both in the area of supporting migration towards aspect-oriented solutions and supporting the development of aspect languages that are better suited for such migrations.Comment: 25 page