Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

Thermally Aware Design Approaches for High Power Density Ultra-Wide Bandgap Power Electronics

Ultra-wide bandgap (UWBG) semiconductors like β-type gallium oxide (β-Ga2O3) show promise for the development of next-generation high power density electronics devices such as RF and power electronics. The large bandgap (4.8 eV), high breakdown fields (8 MV/cm), and excellent thermal stability of β-Ga2O3 give promise to the production of low-loss power switching devices with large breakdown voltage, and potentially allows for high-temperature and deep space operation. However, a major drawback of β-Ga2O3 arises from its poor thermal conductivity, which results in devices with unacceptably high junction-to-package thermal resistance. While there is considerable promise for future devices made from UWBG materials, their adoption as a technology will hinge upon novel approaches to address heat dissipation at the die level which will enable high power density operation. The aims of this thesis are i) to develop novel thermal management strategies to reduce the junction-to-package thermal resistance for devices made from low thermal conductivity UWBG materials for both lateral and vertical devices, ii) to conduct an analysis of architectures for homoepitaxial β-Ga2O3 metal-oxide semiconductor field effect transistors (MOSFETs) to optimize the device thermal performance and verify experimentally, and iii) to optimize thermal management design for both steady-state and transient-state of UWBG transistors. Overall, the optimal thermally-aware design for vertical and lateral structures for steady-state and transient applications will be provided by investigating the device layout such as substrate orientation, configuration of electrodes (number of fingers, channel width, location of metallization pads), dielectric heat spreader, and thermal boundary conductance between metal and β-Ga2O3.Ph.D

Finite Element Method Modeling Of Advanced Electronic Devices

In this dissertation, we use finite element method together with other numerical techniques to study advanced electron devices. We study the radiation properties in electron waveguide structure with multi-step discontinuities and soft wall lateral confinement. Radiation mechanism and conditions are examined by numerical simulation of dispersion relations and transport properties. The study of geometry variations shows its significant impact on the radiation intensity and direction. In particular, the periodic corrugation structure exhibits strong directional radiation. This interesting feature may be useful to design a nano-scale transmitter, a communication device for future nano-scale system. Non-quasi-static effects in AC characteristics of carbon nanotube field-effect transistors are examined by solving a full time-dependent, open-boundary Schrödinger equation. The non-quasi-static characteristics, such as the finite channel charging time, and the dependence of small signal transconductance and gate capacitance on the frequency, are explored. The validity of the widely used quasi-static approximation is examined. The results show that the quasi-static approximation overestimates the transconductance and gate capacitance at high frequencies, but gives a more accurate value for the intrinsic cut-off frequency over a wide range of bias conditions. The influence of metal interconnect resistance on the performance of vertical and lateral power MOSFETs is studied. Vertical MOSFETs in a D2PAK and DirectFET package, and lateral MOSFETs in power IC and flip chip are investigated as the case studies. The impact of various layout patterns and material properties on RDS(on) will provide useful guidelines for practical vertical and lateral power MOSFETs design

Design, Characterization And Analysis Of Electrostatic Discharge (esd) Protection Solutions In Emerging And Modern Technologies

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the en

RF Switch Design

For this project, we created a simulation platform in order to optimize the silicon-on-insulator (SOI), field effect transistor (FET) switch technology. There are many alterations that could make these switches more efficient. However, such alterations are infrequently attempted due to the time-intensive nature of common circuit simulators. The goal was to create a faster way to test design ideas early in the design process. Our platform included a switch model, a transistor model, and a finite element analysis capacitance model

Design, simulation and fabrication of 4H-SiC Power MOSFETs

For a 4H-SiC MOSFET to compete with Si counterparts, especially at lower voltages (1.2kV), the channel resistance contributes to a significant part in the total on-state resistance which must be addressed. Since most of the commercially available SiC wafer materials are grown on the {0001} crystal plane, a trench-gate MOSFET is necessary to take the advantage of the higher reported channel mobility on the {112 ̅ 0} crystal plane. 1.2kV trench MOSFET design and fabrication is the main focus in this work. The micro-trench free dry etching process has first been developed with a systematic study on the dry etching parameters. Trench corner rounding has also been investigated since a rounded corner is normally preferred to avoid an electric field hot spot. Two generations of trench MOSFETs have been designed and fabricated. The 1st generation devices have been used to validate the fabrication process. A maximum breakdown voltage of 1600V has been achieved for the 1st generation devices. The p+ trench bottom shielding region provides the protection for the trench gate oxide since it shifts the peak electric field from the oxide/semiconductor interface to a semiconductor p-n junction; however, it also introduces a parasitic JFET region into the trench MOSFET structure which severely degraded the on-state performance of the 1st generation devices. The 2nd generation devices were designed to eliminate the effect of the parasitic JFET region and improve the on-state performance. The optimised device structure with a current spreading layer (CSL) and p+ implantation clearance in the 2nd generation design has successfully eliminated the effect of the parasitic JFET region. Further design and process optimisation is necessary to increase the current density of the device which was as low as 3A/cm2. A fabrication trial has been carried out on the MOSFETs with integrated Schottky contacts at the termination region and therefore, external Schottky diodes are not necessary for many applications. A 10kV DMOSFET has also been designed and fabricated with maximum breakdown voltage at 13.6kV. The high voltage termination design options have been discussed among the floating field ring (FFR) termination and the junction termination extensions (JTEs). The on-state performance is poor due to a photo mask error on the JFET length which needs to be optimised for the next generation devices. Novel device structures have been studied with simulation. These include trench MOSFET with integrated Schottky diode and 3.3kV superjunction trench MOSFET. The MOSFET with integrated Schottky diode not only reduces the chip area consumption, but also reduces the chip count in the system level. In the proposed design, the Schottky contact is placed at the bottom of the trench structure for the first time. The superjunction structure has a great potential for SiC devices rated at above 3.3kV. The proposed design uses implanted p-pillar with a trench gate structure which combines the benefits of low channel resistance and low drift region resistance