Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

Smart Sensor Networks For Sensor-Neural Interface

One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface. In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5μm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18μm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system. The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Ultra Low Power FM-UWB Transceiver for High-Density Wireless Sensor Networks

The WiseSkin project aims to provide a non-invasive solution for restoration of a natural sense of touch to persons using prosthetic limbs. By embedding sensor nodes into the silicone coating of the prosthesis, which acts as a sensory skin, WiseSkin targets to provide improved gripping, manipulation and mobility for amputees. Flexibility, freedom of movement and comfort demand unobtrusive, highly miniaturized, low-power sensing capabilities built into the artificial skin, which is then integrated with a sensory feedback system. Wireless communication between the sensor nodes provides more flexibility, better scalability and robustness compared to wired solution, and is therefore a preferred approach for WiseSkin. Design of an RF transceiver tailored for the specific needs of WiseSkin is the topic of this work. The properties of FM ultra-wide band (FM-UWB) modulation make it a good candidate for High-Density Wireless Sensor Networks (HD-WSN). The proposed FM-UWB receivers take advantage of short range to reduce power consumption, and exploit robustness of this wideband modulation scheme. The LNA, identified as the biggest consumer, is removed and signal is directly converted to dc, where amplification and demodulation are performed. Owing to 500 MHz bandwidth, frequency offset and phase noise can be tolerated, and a low-power, free-running ring oscillator can be used to generate the LO signal. The receiver is referred to as an approximate zero-IF receiver. Two receiver architectures are studied. The first one performs quadrature downconversion, and owing to the demodulator linearity, provides the multi-user capability. In the second receiver, quadrature demodulation is replaced by the single-ended one. Due to the nature of the demodulator, sensitivity degrades, and multiple FM-UWB signals cannot be resolved, but the consumption is almost halved compared to the first receiver. The proposed approach is verified through two integrations, both in a standard 65 nm bulk CMOS process. In the first run, a standalone quadrature receiver was integrated. Power consumption of 423 uW was measured, while achieving -70 dBm sensitivity. Good narrow-band interference rejection and multiuser capability with up to 4 FM-UWB channels could be achieved. In the second run, a full transceiver is integrated, with both quadrature and single-ended receivers and a transmitter, all sharing a single IO pad, without the need for any external passive components or switches. The quadrature receiver, with on-chip baseband processing and multi-user support, in this case consumes 550 uW, with a sesensitivity of -68 dBm. The low power receiver consumes 267 uW, and provides -57 dBm sensitivity, at a single FM-UWB channel. The implemented trantransmitter transmits a 100 kb/s FM-UWB signal at -11.4 dBm, while drawing 583 uW from the 1 V supply. The on-chip clock recovery allows reference frequency offset up to 8000 ppm. Since state of the art on-chip RC oscillators can provide below 2100 ppm across the temperature range of interest, the implemented transceiver demonstrates the feasibility of a fully integrated FM-UWB radio with no need for a quartz reference or any external components. In addition, the transceiver can tolerate up to 3 dBm narrow-band interferer at 2.4 GHz. Such a strong signal can be used to remotely power the sensor nodes inside the artificial skin and enable a truly wirelessWiseSkin solution

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Towards Very Large Scale Analog (VLSA): Synthesizable Frequency Generation Circuits.

Driven by advancement in integrated circuit design and fabrication technologies, electronic systems have become ubiquitous. This has been enabled powerful digital design tools that continue to shrink the design cost, time-to-market, and the size of digital circuits. Similarly, the manufacturing cost has been constantly declining for the last four decades due to CMOS scaling. However, analog systems have struggled to keep up with the unprecedented scaling of digital circuits. Even today, the majority of the analog circuit blocks are custom designed, do not scale well, and require long design cycles. This thesis analyzes the factors responsible for the slow scaling of analog blocks, and presents a new design methodology that bridges the gap between traditional custom analog design and the modern digital design. The proposed methodology is utilized in implementation of the frequency generation circuits – traditionally considered analog systems. Prototypes covering two different applications were implemented. The first synthesized all-digital phase-locked loop was designed for 400-460 MHz MedRadio applications and was fabricated in a 65 nm CMOS process. The second prototype is an ultra-low power, near-threshold 187-500 kHz clock generator for energy harvesting/autonomous applications. Finally, a digitally-controlled oscillator frequency resolution enhancement technique is presented which allows reduction of quantization noise in ADPLLs without introducing spurs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109027/1/mufaisal_1.pd

Algorithm and Hardware Co-Design for Local/Edge Computing

Advances in VLSI manufacturing and design technology over the decades have created many computing paradigms for disparate computing needs. With concerns for transmission cost, security, latency of centralized computing, edge/local computing are increasingly prevalent in the faster growing sectors like Internet-of-Things (IoT) and other sectors that require energy/connectivity autonomous systems such as biomedical and industrial applications. Energy and power efficient are the main design constraints in local and edge computing. While there exists a wide range of low power design techniques, they are often underutilized in custom circuit designs as the algorithms are developed independent of the hardware. Such compartmentalized design approach fails to take advantage of the many compatible algorithmic and hardware techniques that can improve the efficiency of the entire system. Algorithm hardware co-design is to explore the design space with whole stack awareness. The main goal of the algorithm hardware co-design methodology is the enablement and improvement of small form factor edge and local VLSI systems operating under strict constraints of area and energy efficiency. This thesis presents selected works of application specific digital and mixed-signal integrated circuit designs. The application space ranges from implantable biomedical devices to edge machine learning acceleration

Wireless Transceivers for Implantable Microsystems.

In this thesis, we present the first-ever fully integrated mm3 low-power biomedical transceiver with 1 meter of range that is powered by a mm2 thin-film battery. The transceiver is targeted for biomedical implants where size and energy constraints dictated by application make design challenging. Despite all the previous work in RFID tags, form factor of such radios is incompatible with mm3 biomedical implants. The proposed transceiver bridges this gap by providing a compact low-power solution that can run off small thin-film batteries and can be stacked with other system components in a 3D fashion. On the sensor-to-external side, we proposed a novel FSK architecture based on dual-resonator LC oscillators to mitigate unwanted overlap of two FSK tones’ phase noise spectrum. Due to inherent complexity of such systems, fourth order dual-resonator oscillators can exhibit instable operation. We mathematically modeled the instability and derive design conditions for stable oscillations. Through simulation and measurements, validity of derived models was confirmed. Together with other low-power system blocks, the transmitter was successfully implanted in live mouse and in-vivo measurements were performed to confirm successful transmission of vital signals through organic tissue. The integrated transmitter achieved a bit-error-rate of 10-6 at 10cm with 4.7nJ/bit energy consumption. On the external-to-sensor link, we proposed a new protocol to lower receiver peak power, which is highly limited due to small size of mm3 microsystem battery. In the proposed protocol, sending same data multiple times drastically relaxes jitter requirement on the sensor side at the cost of increased power consumption on the external side without increasing peak power radiated by the external unit. The receiver also uses a dual-coil LNA to improve range by 22% with only 11% area overhead. An asynchronous controller manages protocol timing and limits total monitoring current to 43nA. The fabricated receiver consumes 1.6nJ/bit at 40kbps while positioned 1m away from a 2W source.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102458/1/ghaed_1.pd

Energy-efficient wireless sensors : fewer bits, Moore MEMS

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis. Page 184 blank.Includes bibliographical references (p. 171-183).Adoption of wireless sensor network (WSN) technology could enable improved efficiency across a variety of industries that include building management, agriculture, transportation, and health care. Most of the technical challenges of WSNs can be linked to the stringent energy constraints of each sensor node, where wireless communication and leakage energy are the doninant components of active and idle energy costs. To address these two limitations, this thesis adopts compressed sensing (CS) theory as a generic source coding framework to minimize the transmitted data and proposes the use of micro-electro-mechanical (MEM) relay technology to eliminate the idle leakage. To assess the practicality of adopting CS as a source coding framework we examine the inpact of finite resources, input noise, and wireless channel impairments on the compression and reconstruction performance of CS. We show that CS, despite being a lossy compression algorithm, can realize compression factors greater than loX with no loss in fidelity for sparse signals quantized to medium resolutions. We also model the hardware costs for implementing the CS encoder and results from a test chip designed in a 90 nm CMOS process that consumes only 1.9 [mu]W for operating frequencies below 20 kHz, verifies the models. The encoder is desioned to enable continuous, on-the-fly compression that is demonstrated on electroencephalography (EEG) and electrocardiogram (EKG) signals to show the applicability of CS. To address sub-threshold leakage, which limits the energy performance in CMOS-based sensor nodes, we develop design methodologies towards leveraging the zero leakage characteristics of MEM relays while overcoming their slower switching speeds. Projections on scaled relay circuits show the potential for greater than loX improvements in energy efficieicy over CMOS at up to 10-100 Mops for a variety of circuit sub-systems. Experimental results demonstrating functionality for several circuit building blocks validate the viability of the technology, while feedback from these results is used to refine the device design. Incorporating all of the design elements, w present simnulation results for our most recent test chip design which implements relay-based versions of the CS encoder circuits in a 0.25 jim lithographic process showing 5X improvement over our 90 nm CMOS design.by Fred Chen.Ph.D

Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25µm CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68µW at 2.5V power-supply, 1.69µVrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25µm CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26µVrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18µm CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26µVrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd