Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Subsampling receivers with applications to software defined radio systems

Este trabajo de tesis propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estándar y SDR (Software Defined Radio). El objetivo principal será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, así como la reducción de los costes totales de los receptores de comunicación y de los equipos de certificación que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como la idea de la tecnología SDR es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidores analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarían sin perder resolución para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de sistemas debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando estas arquitecturas, este componente procesará la señal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las técnicas de submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificación de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analógico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso diseñada y fabricada, y cuya caracterización experimental muestra una resolución de más 8 bits para un ancho de banda analógico de 20 MHz. Concretamente, la resolución medida será mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estándares de comunicaciones inalámbricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido térmico) y una dificultad añadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interés, esta tesis propone el uso de una técnica basada en una arquitectura de reloj múltiple con el objetivo de aumentar la resolución y cubrir un número mayor de estándares para su test y certificación. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguirá reducir este efecto, aumentando la resolución en aproximadamente 0.5-1 bit respecto al caso de sólo usar una fuente de reloj. Las expresiones teóricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis también propone novedosas técnicas para la aplicación de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafíos adicionales por el hecho de existir la posibilidad de solapamiento entre la señal de interés y los otros canales de comunicación, así como de solapamiento con sus armónicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo técnicas para la elección de la frecuencia óptima de muestreo que evitan el solapamiento entre señales, a la vez que consiguen incrementar la resolución del receptor. Finalmente, se presentará la optimización en cuanto a características de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estará basado en las técnicas de reloj múltiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema diseñado podrá emplearse para diversas aplicaciones a ambos lados de la cadena de comunicación, tal como en receptores de detección de espectro para radio cognitiva, o implementando el bucle de realimentación de un transmisor para la linealización de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseño de un prototipo de recepción multi-estándar basado en submuestreo para aplicaciones de test y certificación. La segunda aportación es la dedicada a la optimización de las especificaciones de ruido a partir de las técnicas presentadas basadas en reloj múltiple. Por último, la tercera contribución principal es la relacionada con la extensión de este tipo de técnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teóricamente y experimentalmente validadas

Distributed localization of a RF target in NLOS environments

We propose a novel distributed expectation maximization (EM) method for non-cooperative RF device localization using a wireless sensor network. We consider the scenario where few or no sensors receive line-of-sight signals from the target. In the case of non-line-of-sight signals, the signal path consists of a single reflection between the transmitter and receiver. Each sensor is able to measure the time difference of arrival of the target's signal with respect to a reference sensor, as well as the angle of arrival of the target's signal. We derive a distributed EM algorithm where each node makes use of its local information to compute summary statistics, and then shares these statistics with its neighbors to improve its estimate of the target localization. Since all the measurements need not be centralized at a single location, the spectrum usage can be significantly reduced. The distributed algorithm also allows for increased robustness of the sensor network in the case of node failures. We show that our distributed algorithm converges, and simulation results suggest that our method achieves an accuracy close to the centralized EM algorithm. We apply the distributed EM algorithm to a set of experimental measurements with a network of four nodes, which confirm that the algorithm is able to localize a RF target in a realistic non-line-of-sight scenario.Comment: 30 pages, 11 figure

Data Acquisition Applications

Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book

Frontend em tempo real para cognitive radio inspirado na cóclea humana

Mestrado em Engenharia Electrónica e TelecomunicaçõesNesta tese vamos discutir a implementação e desenvolvimento de um frontend inspirado na cóclea humana que é capaz de amostrar sinais RF com uma larga largura de banda e gama dinâmica. Este front-end usa um multiplexer de RF de 8 canais amostrado por uma placa com 8 ADCs a funcionar a 250MSPS. Uma placa de desenvolvimento com uma FPGA controla a ADC e implementa os ltros de síntese digitais e liga a um computador pessoal para transferir toda a informação e mudar os coe cientes dos ltros em tempo real.In this thesis it will be discussed the real time implementation and development of a front-end inspired by the Human Cochlea that is able to sample RF signals with a large bandwidth and dynamic range. This front-end uses an 8 channel RF multiplexer sampled by an 8 channel 250MSPS ADC board. A FPGA board controls the ADC, implements the digital synthesis lter bank and connects to a personal computer to transfer the data and to change the lters in real-time

Estudo do impacto da distorção não-linear em arquitecturas de recepção rádio

Doutoramento em Engenharia ElectrotécnicaA dissertação de doutoramento apresentada insere-se na área de electrónica não-linear de rádio-frequência (RF), UHF e microondas, tendo como principal campo de acção o estudo da distorção nãolinear em arquitecturas de recepção rádio, nomeadamente receptores de conversão directa como Power Meters, RFID (Radio Frequency IDentification) ou SDR (Software Define Radio) front-ends. Partindo de um estudo exaustivo das actuais arquitecturas de recepção de radiofrequência e revendo todos os conceitos teóricos relacionados com o desempenho não-linear dos sistemas/componentes electrónicos, foram desenvolvidos algoritmos matemáticos de modulação dos comportamentos não-lineares destas arquitecturas, simulados e testados em laboratório e propostas novas arquitecturas para a minimização ou cancelamento do impacto negativo de grandes interferidores em frequências vizinhas ao do sistema pretendido.The doctoral dissertation presented is inserted in the area of electronic non-linear radio frequency (RF), microwave and UHF, with the main field of action focus in the study of nonlinear distortion in radio reception architectures, including direct-conversion receivers like Power Meters, RFID (Radio Frequency Identification) or SDR (Software Defined Radio) front-ends. Started with on an exhaustive study of current radio reception architectures and the review from all the theoretical concepts related to nonlinear systems / electronics, it were developed mathematical algorithms for modulating the nonlinear behaviour of these architectures, simulated and tested in the laboratory and proposed new architectures for reduction or cancellation of the negative impact of large jammers at frequencies surrounding the system of choice

Modulation, Coding, and Receiver Design for Gigabit mmWave Communication

While wireless communication has become an ubiquitous part of our daily life and the world around us, it has not been able yet to deliver the multi-gigabit throughput required for applications like high-definition video transmission or cellular backhaul communication. The throughput limitation of current wireless systems is mainly the result of a shortage of spectrum and the problem of congestion. Recent advancements in circuit design allow the realization of analog frontends for mmWave frequencies between 30GHz and 300GHz, making abundant unused spectrum accessible. However, the transition to mmWave carrier frequencies and GHz bandwidths comes with new challenges for wireless receiver design. Large variations of the channel conditions and high symbol rates require flexible but power-efficient receiver designs. This thesis investigates receiver algorithms and architectures that enable multi-gigabit mmWave communication. Using a system-level approach, the design options between low-power time-domain and power-hungry frequency-domain signal processing are explored. The system discussion is started with an analysis of the problem of parameter synchronization in mmWave systems and its impact on system design. The proposed synchronization architecture extends known synchronization techniques to provide greater flexibility regarding the operating environments and for system efficiency optimization. For frequency-selective environments, versatile single-carrier frequency domain equalization (SC-FDE) offers not only excellent channel equalization, but also the possibility to integrate additional baseband tasks without overhead. Hence, the high initial complexity of SC-FDE needs to be put in perspective to the complexity savings in the other parts of the baseband. Furthermore, an extension to the SC-FDE architecture is proposed that allows an adaptation of the equalization complexity by switching between a cyclic-prefix mode and a reduced block length overlap-save mode based on the delay spread. Approaching the problem of complexity adaptation from time-domain, a high-speed hardware architecture for the delayed decision feedback sequence estimation (DDFSE) algorithm is presented. DDFSE uses decision feedback to reduce the complexity of the sequence estimation and allows to set the system performance between the performance of full maximum-likelihood detection and pure decision feedback equalization. An implementation of the DDFSE architecture is demonstrated as part of an all-digital IEEE802.11ad baseband ASIC manufactured in 40nm CMOS. A flexible architecture for wideband mmWave receivers based on complex sub-sampling is presented. Complex sub-sampling combines the design advantages of sub-sampling receivers with the flexibility of direct-conversion receivers using a single passive component and a digital compensation scheme. Feasibility of the architecture is proven with a 16Gb/s hardware demonstrator. The demonstrator is used to explore the potential gain of non-equidistant constellations for high-throughput mmWave links. Specifically crafted amplitude phase-shift keying (APSK) modulation achieve 1dB average mutual information (AMI) advantage over quadrature amplitude modulation (QAM) in simulation and on the testbed hardware. The AMI advantage of APSK can be leveraged for a practical transmission using Polar codes which are trained specifically for the constellation