Experiments with embedded system design at UMinho and AIT

Nowadays, embedded systems are central to modern life, mainly due to the scientific and technological advances of the last decades that started a new reality in which the embedded systems market has been growing steadily, along with a monthly or even weekly emergence of new products with different applications across several domains. This embedded system ubiquity was the drive for the following question ”Why should we focus on embedded systems design?” that was answered in [1, 2] with the following points: (1) high and fast penetration in products and services due to the integration of networking, operating system and database capabilities, (2) very strategic field economically and (3) a new and relatively undefined subject in academic environment. Other adja- cent questions have been raised such as ”Why is the design of embedded systems special?”. The answer for this last question is based mainly on several problems raised by the new technologies, such as the need for more human resources in specialized areas and high learning curve for system designers. As pointed in [1], these problems can prevent many companies from adopting these new technologies or force them not to respond timely in mastering these technological and market challenges. In this paper, it is described how staff at ESRG-UMinho 1 and ISE-AIT 2 faced the embedded systems challenges at several levels. It starts to de- scribe the development of the educational context for the new technolo- gies and show how our Integrated Master Curriculum in Industrial Elec- tronics and Computer Engineering has been adapted to satisfy the needs of the major university customers, the industry

Design Space Exploration: Bridging the Gap Between High­‐Level Models and Virtual ExecutionPlatforms

International audienceThispaper presents a novel embedded systems modeling framework that fills the gap betweenhigh-­‐level AADL models and low-­‐level hardware virtual execution platforms. This approach allows refinement and improvement of system performance through exploration of architectures at different levels of abstraction. The aim of the proposed approach is to achieve virtual prototyping of the complete system in order to allow validation to begin early in the design flow, thereby accelerating its development while improving system performances

A Unifying View of Loosely Time-Triggered Architectures

Cyber-Physical Systems require distributed architectures to support safety critical real-time control. Hermann Kopetz' Time-Triggered Architecture (TTA) has been proposed as both an architecture and a comprehensive paradigm for systems architecture, for such systems. TTA offers the programmer a logical discrete time compliant with synchronous programming, together with timing bounds. A clock synchronization protocol is required, unless the local clocks used themselves provide the recquired accuracy. To relax the strict requirements on synchronization imposed by TTA, Loosely Time-Triggered Architectures (LTTA) have been proposed. In LTTA, computation and communication units are all triggered by autonomous, unsynchronized, clocks. Communication media act as shared memories between writers and readers and communication is non blocking. This is at the price of communication artifacts (such as duplication or loss of data), which must be compensated for by using some "LTTA protocol". In this paper we pursue our previous work by providing a unified presentation of the two variants of LTTA (token- and time-based), with simplified analyses. We compare these two variants regarding performance and robustness and we provide ways to combine them. This report was prepared for a lecture in Gérard Berry's seminar series at the Collège de France, March 5, 2014; it is a corrected version of a paper, which appeared at Emsoft'2010. It is dedicated to our close friend Paul Caspi who died in April 2012.Les infrastructures de calcul distribuées pour le contrôle des systèmes embarqués critiques requièrent des propriétés particulières destinées à préserver les caractéristiques attendues du contrôleur. Les architectures TTA (Time-Triggered Architectures) ont été proposées par Hermann Kopetz, à la fois comme une architecture de calcul et comme une méthodologie de conception des systèmes. TTA offre au programmeur un temps logique conforme à celui de la programmation synchrone, avec en outre un contrôle strict du temps. Il requiert un protocole de synchronisation entre les horloges du système réparti. Pour affaiblir ces hypothèses, les architectures LTTA (Loosely Time-Triggered Architectures) ont été proposées récemment. Dans LTTA, les calculs et les communications sont rythmées par des horloges locales, non synchronisées. Les supports de communication se comportent comme des mémoires partagées. La communication est donc non-bloquante. Ce type de communiccation crée évidemment des artefacts à combattre par un protocole dit "LTTA". Dans cet article nous présentons une approche unifiée des deux techniques connues pour ce type de protocole, reposant sur l'usage, soit de jetons, soit du temps. On compare ces deux variantes et on étudie leur performance. Le présent rapport est une version corrigée d'un article paru à Emsoft'2010. Il est dédié à notre très cher ami Paul Caspi, décédé en Avril 2012

A Unifying View of Loosely Time-Triggered Architectures

Cyber-Physical Systems require distributed architectures to support safety critical real-time control. Hermann Kopetz' Time-Triggered Architecture (TTA) has been proposed as both an architecture and a comprehensive paradigm for systems architecture, for such systems. TTA offers the programmer a logical discrete time compliant with synchronous programming, together with timing bounds. A clock synchronization protocol is required, unless the local clocks used themselves provide the recquired accuracy. To relax the strict requirements on synchronization imposed by TTA, Loosely Time-Triggered Architectures (LTTA) have been proposed. In LTTA, computation and communication units are all triggered by autonomous, unsynchronized, clocks. Communication media act as shared memories between writers and readers and communication is non blocking. This is at the price of communication artifacts (such as duplication or loss of data), which must be compensated for by using some "LTTA protocol". In this paper we pursue our previous work by providing a unified presentation of the two variants of LTTA (token- and time-based), with simplified analyses. We compare these two variants regarding performance and robustness and we provide ways to combine them. This report was prepared for a lecture in Gérard Berry's seminar series at the Collège de France, March 5, 2014; it is a corrected version of a paper, which appeared at Emsoft'2010. It is dedicated to our close friend Paul Caspi who died in April 2012.Les infrastructures de calcul distribuées pour le contrôle des systèmes embarqués critiques requièrent des propriétés particulières destinées à préserver les caractéristiques attendues du contrôleur. Les architectures TTA (Time-Triggered Architectures) ont été proposées par Hermann Kopetz, à la fois comme une architecture de calcul et comme une méthodologie de conception des systèmes. TTA offre au programmeur un temps logique conforme à celui de la programmation synchrone, avec en outre un contrôle strict du temps. Il requiert un protocole de synchronisation entre les horloges du système réparti. Pour affaiblir ces hypothèses, les architectures LTTA (Loosely Time-Triggered Architectures) ont été proposées récemment. Dans LTTA, les calculs et les communications sont rythmées par des horloges locales, non synchronisées. Les supports de communication se comportent comme des mémoires partagées. La communication est donc non-bloquante. Ce type de communiccation crée évidemment des artefacts à combattre par un protocole dit "LTTA". Dans cet article nous présentons une approche unifiée des deux techniques connues pour ce type de protocole, reposant sur l'usage, soit de jetons, soit du temps. On compare ces deux variantes et on étudie leur performance. Le présent rapport est une version corrigée d'un article paru à Emsoft'2010. Il est dédié à notre très cher ami Paul Caspi, décédé en Avril 2012

A Model-Based Development and Verification Framework for Distributed System-on-Chip Architecture

The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.Siirretty Doriast

The Early Assessment of System Performance in Distributed Real-time Systems

Distributed real-time process control systems are notoriously difficult to develop. They frequently overrun time schedules and break cost constraints. The problems are compounded where there are multiple development teams and stakeholders. Conventional model-driven development has been examined to see if it can be extended to resolve some of these problems. It may be possible to use early system design stages to identify performance issues which would otherwise not be identified until late in the development of the system. A functional model is proposed, in addition to those conventionally used for model-driven development, based on loosely coupled functional elements, to represent the behaviour of each system component. The model complements existing requirements and design specifications and addresses the combination of individual component abstractions to produce a complete system specification. The functional model enables the accurate prediction of system performance prior to the detailed design of each component. The thesis examines how performance can be calculated and modelled. An animator tool and associated code generator are used to predict system and component performance in a distributed aircraft navigation system. The use of the animator to support the system design prior to the generation of the component contract specifications and interface control documents provides a means of assessing performance which is accessible to domain experts and system designers alike. The model also enables the effects of requirements changes and component design issues on the system design to be assessed in terms of the system design to provide system wide solutions. This performance assessment model and animator compliments the existing 'fix-it-later' approach, reducing the chances of performance failure detected late during the system development process when they are most expensive to fix

Towards a Model-Centric Software Testing Life Cycle for Early and Consistent Testing Activities

The constant improvement of the available computing power nowadays enables the accomplishment of more and more complex tasks. The resulting implicit increase in the complexity of hardware and software solutions for realizing the desired functionality requires a constant improvement of the development methods used. On the one hand over the last decades the percentage of agile development practices, as well as testdriven development increases. On the other hand, this trend results in the need to reduce the complexity with suitable methods. At this point, the concept of abstraction comes into play, which manifests itself in model-based approaches such as MDSD or MBT. The thesis is motivated by the fact that the earliest possible detection and elimination of faults has a significant influence on product costs. Therefore, a holistic approach is developed in the context of model-driven development, which allows applying testing already in early phases and especially on the model artifacts, i.e. it provides a shift left of the testing activities. To comprehensively address the complexity problem, a modelcentric software testing life cycle is developed that maps the process steps and artifacts of classical testing to the model-level. Therefore, the conceptual basis is first created by putting the available model artifacts of all domains into context. In particular, structural mappings are specified across the included domain-specific model artifacts to establish a sufficient basis for all the process steps of the life cycle. Besides, a flexible metamodel including operational semantics is developed, which enables experts to carry out an abstract test execution on the modellevel. Based on this, approaches for test case management, automated test case generation, evaluation of test cases, and quality verification of test cases are developed. In the context of test case management, a mechanism is realized that enables the selection, prioritization, and reduction of Test Model artifacts usable for test case generation. I.e. a targeted set of test cases is generated satisfying quality criteria like coverage at the model-level. These quality requirements are accomplished by using a mutation-based analysis of the identified test cases, which builds on the model basis. As the last step of the model-centered software testing life cycle two approaches are presented, allowing an abstract execution of the test cases in the model context through structural analysis and a form of model interpretation concerning data flow information. All the approaches for accomplishing the problem are placed in the context of related work, as well as examined for their feasibility by of a prototypical implementation within the Architecture And Analysis Framework. Subsequently, the described approaches and their concepts are evaluated by qualitative as well as quantitative evaluation. Moreover, case studies show the practical applicability of the approach

Élaboration d'une méthodologie de conception des systèmes embarqués basée sur la transformation du modèle fonctionnel de haut niveau vers le prototype virtuel

La croissance rapide des progrès technologiques combinée aux demandes exigeantes de l’industrie entraîne une augmentation de la complexité des systèmes embarqués. Cette complexité impose plusieurs contraintes et critères à respecter pour produire des systèmes compétitifs et robustes. Aussi, les méthodologies de conception ont grandement évolué au cours des dernières années pour encadrer le développement de ces systèmes complexes et assurer leur conformité aux requis initiaux. C’est ainsi que de nouvelles approches basées sur des modèles sont apparues, pour pallier à ces difficultés et maîtriser le niveau de complexité. Mais souvent ces approches basées sur des modèles traitent les aspects fonctionnels et logiciels du système sans prendre en considération les aspects d’exécution sur de réelles plateformes matérielles. Les travaux développés dans le cadre de ce projet de recherche visent à mettre en oeuvre une nouvelle méthodologie de conception des systèmes embarqués. Cette méthodologie permet d’établir un lien entre le niveau fonctionnel des modèles et la plateforme d’exécution matérielle de l’application en question. L’approche développée est basée sur l’utilisation du langage de modélisation AADL pour décrire le comportement logiciel du système embarqué à un haut niveau d’abstraction. Ensuite, une chaîne de transformation automatique convertit le modèle AADL vers un modèle SystemC. Finalement, l’environnement Space Studio est utilisé pour construire un prototype virtuel de la plateforme. Cet environnement permet l’exécution des aspects fonctionnels du système sur des ressources matérielles. Les performances du système peuvent ainsi être validées et raffinées en se basant sur une exploration architecturale de la plateforme matérielle. Une application d’imagerie a été exploitée en tant qu’étude de cas pour expérimenter ce flot. Il s’agit d’une application de décodage vidéo MJPEG (Motion JPEG). Durant l’expérimentation, un modèle AADL de l’application MJPEG a été développé décrivant son comportement fonctionnel. Ensuite, la chaîne de transformation utilisée traduit automatiquement le modèle AADL en un modèle SystemC. Le modèle SystemC a servi comme élément de base représentant l’aspect logiciel dans l’environnement de prototypage virtuel et de conception conjointe Space Studio. L’outil Space Studio s’est montré utile en permettant la création rapide d’un prototype de plateforme matérielle d’exécution, le partitionnement des fonctions logicielles sur des ressources matérielles et la validation et raffinement des performances du système. Les résultats d’expérimentation obtenus furent concluants. La vitesse d’exécution a été visiblement augmentée et le temps pris pour achever la simulation du système a été réduit de 81.86%. En ce qui concerne le taux d’occupation du processeur quant à lui a considérablement diminué, ce qui pourra ainsi diminuer le taux de puissance consommée par les ressources matérielles. Ainsi le traitement de données par unité de temps s’est amélioré 12 fois de plus après le raffinement porté sur l’assignement des fonctions logicielles sur la plateforme matérielle. Dans le cadre de ce projet, un article scientifique a été publié (Benyoussef et al., Février 2014) à la conférence ERTS 2014 (Embedded Real Time Software and Systems). Ce travail présente le contexte et la problématique liée aux méthodologies basées sur des modèles, la nouvelle approche de modélisation développée ainsi qu’une preuve de concept avec une application de décodage MJPEG