Scalable algorithms for software based self test using formal methods

textTransistor scaling has kept up with Moore's law with a doubling of the number of transistors on a chip. More logic on a chip means more opportunities for manufacturing defects to slip in. This, in turn, has made processor testing after manufacturing a significant challenge. At-speed functional testing, being completely non-intrusive, has been seen as the ideal way of testing chips. However for processor testing, generating instruction level tests for covering all faults is a challenge given the issue of scalability. Data-path faults are relatively easier to control and observe compared to control-path faults. In this research we present a novel method to generate instruction level tests for hard to detect control-path faults in a processor. We initially map the gate level stuck-at fault to the Register Transfer Level (RTL) and build an equivalent faulty RTL model. The fault activation and propagation constraints are captured using Control and Data Flow Graphs of the RTL as a Liner Temporal Logic (LTL) property. This LTL property is then negated and given to a Bounded Model Checker based on a Bit-Vector Satisfiability Module Theories (SMT) solver. From the counter-example to the property we can extract a sequence of instructions that activates the gate level fault and propagates the fault effect to one of the observable points in the design. Other than the user supplying instruction constraints, this approach is completely automatic and does not require any manual intervention. Not all the design behaviors are required to generate a test for a fault. We use this insight to scale our previous methodology further. Underapproximations are design abstractions that only capture a subset of the original design behaviors. The use of RTL for test generation affords us two types of under-approximations: bit-width reduction and operator approximation. These are abstractions that perform reductions based on semantics of the RTL design. We also explore structural reductions of the RTL, called path based search, where we search through error propagation paths incrementally. This approach increases the size of the test generation problem step by step. In this way the SMT solver searches through the state space piecewise rather than doing the entire search at once. Experimental results show that our methods are robust and scalable for generating functional tests for hard to detect faults.Electrical and Computer Engineerin

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Синтез самопроверяемых комбинационных устройств на основе кодов с эффективным обнаружением симметричных ошибок

The methods of fault-tolerant coding are often used in the designing of reliable and safety components of automatic control systems: both in the data transmission between system nodes, and at the level of hardware and software architecture. The redundant coding is widely used in the management of combinational logic devices control. In this case, codes, which are oriented to the error detection rather than correction of this, are in use. Such features of codes make it possible to implement the checkable automation systems with acceptable redundancy, which does not exceed the redundancy in the situation of duplication using. The paper highlights the method of the synthesis of self-checking combinational devices, which makes it possible to take into account the features of the source devices architecture, as well as the properties of error detection by redundant codes in solving the problem of the synthesis of technical means for diagnosis. The paper gives the basic information on the theory of the checkable digital systems synthesis on the basis of redundant codes with summation. The basic stages of the analysis of the diagnosis objects topologies are determined with the selection of groups of outputs — groups of structurally and functionally symmetrically independent devices outputs. The formulas are given to determine the presence or the absence of a symmetrical dependence of the diagnosis object outputs. The example illustrating the calculation process is given. The main stages of the analysis of the redundant codes application in the error detection on the functionally symmetric dependent outputs are formulated. The algorithm of the synthesis of the self-checking combinational devices with taking into account the object of diagnosis structure features and the redundant codes properties is proposed.При создании надежных и безопасных компонентов систем автоматического управления часто используются методы помехоустойчивого кодирования — как при передаче данных между узлами системы, так и на уровне архитектуры аппаратных и программных средств. Широко применяется избыточное кодирование при организации контроля комбинационных логических устройств. При этом используются коды, ориентированные именно на обнаружение, а не исправление ошибок. Такие особенности кодов позволяют реализовывать контролепригодные системы автоматики с приемлемой избыточностью, не превышающей избыточности при использовании дублирования. В статье освещается метод синтеза самопроверяемых комбинационных устройств, позволяющий учитывать при решении задачи синтеза технических средств диагностирования особенности архитектуры исходных устройств, а также свойства обнаружения ошибок избыточными кодами. Даются базовые сведения из теории синтеза контролепригодных дискретных систем на основе избыточных кодов с суммированием. Определены ключевые этапы анализа топологий объектов диагностирования с выделением специальных групп выходов — групп структурно и функционально симметрично независимых выходов устройств. Приводятся формулы, позволяющие установить наличие или отсутствие симметричной зависимости выходов объекта диагностирования. Дается пример, иллюстрирующий процесс вычислений. Сформулированы основные этапы анализа применения избыточных кодов при выявлении ошибок на функционально симметрично зависимых выходах. Дан алгоритм синтеза самопроверяемых логических устройств с учетом особенностей структуры объекта диагностирования и свойств избыточных кодов