Study of spin-scan imaging for outer planets missions

The constraints that are imposed on the Outer Planet Missions (OPM) imager design are of critical importance. Imager system modeling analyses define important parameters and systematic means for trade-offs applied to specific Jupiter orbiter missions. Possible image sequence plans for Jupiter missions are discussed in detail. Considered is a series of orbits that allow repeated near encounters with three of the Jovian satellites. The data handling involved in the image processing is discussed, and it is shown that only minimal processing is required for the majority of images for a Jupiter orbiter mission

Efficient Path Delay Test Generation with Boolean Satisfiability

This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

Status of Muon Collider Research and Development and Future Plans

The status of the research on muon colliders is discussed and plans are outlined for future theoretical and experimental studies. Besides continued work on the parameters of a 3-4 and 0.5 TeV center-of-mass (CoM) energy collider, many studies are now concentrating on a machine near 0.1 TeV (CoM) that could be a factory for the s-channel production of Higgs particles. We discuss the research on the various components in such muon colliders, starting from the proton accelerator needed to generate pions from a heavy-Z target and proceeding through the phase rotation and decay ($\pi \to \mu \nu_{\mu}$) channel, muon cooling, acceleration, storage in a collider ring and the collider detector. We also present theoretical and experimental R & D plans for the next several years that should lead to a better understanding of the design and feasibility issues for all of the components. This report is an update of the progress on the R & D since the Feasibility Study of Muon Colliders presented at the Snowmass'96 Workshop [R. B. Palmer, A. Sessler and A. Tollestrup, Proceedings of the 1996 DPF/DPB Summer Study on High-Energy Physics (Stanford Linear Accelerator Center, Menlo Park, CA, 1997)].Comment: 95 pages, 75 figures. Submitted to Physical Review Special Topics, Accelerators and Beam

E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods

During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation. Our results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours (9 hours on average) we can automatically narrow the location of the bug to (the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on average for a design with ~ 1 Million flip-flops) and also obtain the corresponding bug trace. The area impact of E-QED is ~2.5%. In contrast, deter-mining this same information might take weeks (or even months) of mostly manual work using traditional approaches

Techniques for Improving Security and Trustworthiness of Integrated Circuits

The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuit’s gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects

Can bone compaction improve primary implant stability? An in vitro comparative study with osseodensification technique

Background: This study aims to analyze bone compaction and osseodensification techniques and to investigate how cancellous bone compaction could influence primary implant stability (PS). Methods: Two different surgical protocols (bone compactors—BC; osseodensification drills—OD) were compared by placing 20 implants into 20 fresh pig ribs for each procedure. Peak insertion torque (PIT) and peak removal torque (PRT) were investigated using an MGT-12 digital torque gauge, and implant stability quotient (ISQ) was analyzed using an Osstell® Beacon device. Results: Analysis of our data (T-test p < 0.05) evidenced no statistically significant difference between BC and OD in terms of PIT (p = 0.33) or ISQ (p = 0.97). The comparison of PRT values showed a statistically significant difference between BC and OD protocols (p = 0.009). Conclusions: Cancellous bone compaction seems to improve PS, preserving a significant amount of bone and evenly spreading trabeculae on the entire implant site. Although the PIT and ISQ values obtained are similar, the PRT values suggest a better biological response from the surrounding bone tissue. Nevertheless, a larger sample and further in vivo studies are necessary to validate the usefulness of this protocol in several clinical settings

Design of On-Chip Self-Testing Signature Register

Over the last few years, scan test has turn out to be too expensive to implement for industry standard designs due to increasing test data volume and test time. The test cost of a chip is mainly governed by the resource utilization of Automatic Test Equipment (ATE). Also, it directly depends upon test time that includes time required to load test program, to apply test vectors and to analyze generated test response of the chip. An issue of test time and data volume is increasingly appealing designers to use on-chip test data compactors, either on input side or output side or both. Such techniques significantly address the former issues but have little hold over increasing number of input-outputs under test mode. Further, test pins on DUT are increasing over the generations. Thus, scan channels on test floor are falling short in number for placement of such ICs. To address issues discussed above, we introduce an on-chip self-testing signature register. It comprises a response compactor and a comparator. The compactor compacts large chunk of response data to a small test signature whereas the comparator compares this test signature with desired one. The overall test result for the design is generated on single output pin. Being no storage of test response is demanded, the considerable reduction in ATE memory can be observed. Also, with only single pin to be monitored for test result, the number of tester channels and compare edges on ATE side significantly reduce at the end of the test. This cuts down maintenance and usage cost of test floor and increases its life time. Furthermore reduction in test pins gives scope for DFT engineers to increase number of scan chains so as to further reduce test time

A Robotic System for In-Situ Measurement of Soil Total Carbon and Nitrogen

Surges in the cost of fertilizer in recent times coupled with the environmental effects of their over-application have driven the need for farmers to optimize the amount of fertilizer they apply on the farm. One of the key steps in determining the right amount of fertilizer to apply in a given field is measuring the amount of nutrients present in the soil. To ascertain nutrient deficiencies, most farmers perform wet chemistry analysis of soil samples which requires a lot of time and is expensive. In this research project, a robotic system was designed and developed that could autonomously move to predetermined GPS waypoints and estimate total carbon (TC) and total nitrogen (TN) content in the soil in-situ using visible and near-infrared reflectance spectroscopy - a faster and cheaper method to determine soil nutrients in real-time. For the locomotion of the robotic system, a Husky robotic platform by Clearpath Robotics was used. A Gen2 robotic arm by Kinova Robotics was used for the precise positioning of the probe in taking soil spectral measurement. The probe was custom designed and built to be used in conjunction with the robotic arm as an end-effector. Two lightweight and inexpensive spectrometers by OceanInsight, namely, Flame VisNIR and Flame NIR+, were used to capture the spectral signatures of soil. The prediction was done with a spectroscopic calibration model and External Parameter Orthogonalization (EPO) was applied to remove the moisture effect from the soil spectra. The robotic system was tested at University of Nebraska-Lincoln (UNL) NU-Spidercam phenotyping facility. Two sets of spectra were obtained from the field campaign: in-situ and dry-ground spectra. The dry-ground spectra were used as library scans and Partial Least Square Regression (PLSR) was used for the modeling. The in-situ spectra were randomly divided into EPO calibration and validation sets. Satisfactory results were obtained from the initial prediction on dry-ground validation set, with R2 (coefficient of determination) of 0.77 and RMSE (Root Mean Squared Error) of 0.15% for TC and R2 of 0.64 and RMSE of 171 ppm for TN. There was a reduction in R2 and an increase in RMSE values for both TC and TN when prediction was done directly on the in-situ validation set. For TC, the R2 dropped and RMSE increased to 0.25 and 0.29% respectively, and for TN, the R2 dropped and RMSE increased to 0.19 and 259 ppm respectively. This was primarily due to the presence of moisture in the field samples. The R2 increased to 0.62 and RMSE decreased to 0.2% for TC, and the R2 increased to 0.51 and RMSE decreased to 200 ppm for TN, when EPO was applied on both the in-situ validation and dry-ground sets. These findings highlight the importance of accounting for moisture effects in the prediction of soil properties using the robotic system and demonstrate the potential of the system in enabling soil monitoring and analysis in-situ. Advisor: Yufeng G

Quantifiable Assurance: From IPs to Platforms

Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security and fix the vulnerabilities at earlier design phases, such as Register Transfer Level (RTL) and gate level. The focus of the existing security assessment techniques is mainly twofold. First, they check the security of Intellectual Property (IP) blocks separately. Second, they aim to assess the security against individual threats considering the threats are orthogonal. We argue that IP-level security assessment is not sufficient. Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC), where each IP is surrounded by other IPs connected through glue logic and shared/private buses. Hence, we must develop a methodology to assess the platform-level security by considering both the IP-level security and the impact of the additional parameters introduced during platform integration. Another important factor to consider is that the threats are not always orthogonal. Improving security against one threat may affect the security against other threats. Hence, to build a secure platform, we must first answer the following questions: What additional parameters are introduced during the platform integration? How do we define and characterize the impact of these parameters on security? How do the mitigation techniques of one threat impact others? This paper aims to answer these important questions and proposes techniques for quantifiable assurance by quantitatively estimating and measuring the security of a platform at the pre-silicon stages. We also touch upon the term security optimization and present the challenges for future research directions