PyHGL: A Python-based Hardware Generation Language Framework

Hardware generation languages (HGLs) increase hardware design productivity by creating parameterized modules and test benches. Unfortunately, existing tools are not widely adopted due to several demerits, including limited support for asynchronous circuits and unknown states, lack of concise and efficient language features, and low integration of simulation and verification functions. This paper introduces PyHGL, an open-source Python framework that aims to provide a simple and unified environment for hardware generation, simulation, and verification. PyHGL language is a syntactical superset of Python, which greatly reduces the lines of code (LOC) and improves productivity by providing unique features such as dynamic typing, vectorized operations, and automatic port deduction. In addition, PyHGL integrates an event-driven simulator that simulates the asynchronous behaviors of digital circuits using three-state logic. We also propose an algorithm that eliminates the calculation and transmission overhead of unknown state propagation for binary stimuli. The results suggest that PyHGL code is up to 6.1x denser than traditional RTL and generates high-quality synthesizable RTL code. Moreover, the optimized simulator achieves 2.9x speed up and matches the performance of a commonly used open-source logic simulator

SUE: A Special Purpose Computer for Spin Glass Models

The use of last generation Programmable Electronic Components makes possible the construction of very powerful and competitive special purpose computers. We have designed, constructed and tested a three-dimensional Spin Glass model dedicated machine, which consists of 12 identical boards. Each single board can simulate 8 different systems, updating all the systems at every clock cycle. The update speed of the whole machine is 217ps/spin with 48 MHz clock frequency. A device devoted to fast random number generation has been developed and included in every board. The on-board reprogrammability permits us to change easily the lattice size, or even the update algorithm or the action. We present here a detailed description of the machine and the first runs using the Heat Bath algorithm.Comment: Submitted to Computer Physics Communications, 19 pages, 5 figures, references adde

An Integrated Test Plan for an Advanced Very Large Scale Integrated Circuit Design Group

VLSI testing poses a number of problems which includes the selection of test techniques, the determination of acceptable fault coverage levels, and test vector generation. Available device test techniques are examined and compared. Design rules should be employed to assure the design is testable. Logic simulation systems and available test utilities are compared. The various methods of test vector generation are also examined. The selection criteria for test techniques are identified. A table of proposed design rules is included. Testability measurement utilities can be used to statistically predict the test generation effort. Field reject rates and fault coverage are statistically related. Acceptable field reject rates can be achieved with less than full test vector fault coverage. The methods and techniques which are examined form the basis of the recommended integrated test plan. The methods of automatic test vector generation are relatively primitive but are improving

Content addressable memory project

A parameterized version of the tree processor was designed and tested (by simulation). The leaf processor design is 90 percent complete. We expect to complete and test a combination of tree and leaf cell designs in the next period. Work is proceeding on algorithms for the computer aided manufacturing (CAM), and once the design is complete we will begin simulating algorithms for large problems. The following topics are covered: (1) the practical implementation of content addressable memory; (2) design of a LEAF cell for the Rutgers CAM architecture; (3) a circuit design tool user's manual; and (4) design and analysis of efficient hierarchical interconnection networks

Solving constraint-satisfaction problems with distributed neocortical-like neuronal networks

Finding actions that satisfy the constraints imposed by both external inputs and internal representations is central to decision making. We demonstrate that some important classes of constraint satisfaction problems (CSPs) can be solved by networks composed of homogeneous cooperative-competitive modules that have connectivity similar to motifs observed in the superficial layers of neocortex. The winner-take-all modules are sparsely coupled by programming neurons that embed the constraints onto the otherwise homogeneous modular computational substrate. We show rules that embed any instance of the CSPs planar four-color graph coloring, maximum independent set, and Sudoku on this substrate, and provide mathematical proofs that guarantee these graph coloring problems will convergence to a solution. The network is composed of non-saturating linear threshold neurons. Their lack of right saturation allows the overall network to explore the problem space driven through the unstable dynamics generated by recurrent excitation. The direction of exploration is steered by the constraint neurons. While many problems can be solved using only linear inhibitory constraints, network performance on hard problems benefits significantly when these negative constraints are implemented by non-linear multiplicative inhibition. Overall, our results demonstrate the importance of instability rather than stability in network computation, and also offer insight into the computational role of dual inhibitory mechanisms in neural circuits.Comment: Accepted manuscript, in press, Neural Computation (2018

Spatiotemporal dynamics of the postnatal developing primate brain transcriptome.

Developmental changes in the temporal and spatial regulation of gene expression drive the emergence of normal mature brain function, while disruptions in these processes underlie many neurodevelopmental abnormalities. To solidify our foundational knowledge of such changes in a primate brain with an extended period of postnatal maturation like in human, we investigated the whole-genome transcriptional profiles of rhesus monkey brains from birth to adulthood. We found that gene expression dynamics are largest from birth through infancy, after which gene expression profiles transition to a relatively stable state by young adulthood. Biological pathway enrichment analysis revealed that genes more highly expressed at birth are associated with cell adhesion and neuron differentiation, while genes more highly expressed in juveniles and adults are associated with cell death. Neocortex showed significantly greater differential expression over time than subcortical structures, and this trend likely reflects the protracted postnatal development of the cortex. Using network analysis, we identified 27 co-expression modules containing genes with highly correlated expression patterns that are associated with specific brain regions, ages or both. In particular, one module with high expression in neonatal cortex and striatum that decreases during infancy and juvenile development was significantly enriched for autism spectrum disorder (ASD)-related genes. This network was enriched for genes associated with axon guidance and interneuron differentiation, consistent with a disruption in the formation of functional cortical circuitry in ASD

AMPA experimental communications systems

The program was conducted to demonstrate the satellite communication advantages of Adaptive Phased Array Technology. A laboratory based experiment was designed and implemented to demonstrate a low earth orbit satellite communications system. Using a 32 element, L-band phased array augmented with 4 sets of weights (2 for reception and 2 for transmission) a high speed digital processing system and operating against multiple user terminals and interferers, the AMPA system demonstrated: communications with austere user terminals, frequency reuse, communications in the face of interference, and geolocation. The program and experiment objectives are described, the system hardware and software/firmware are defined, and the test performed and the resultant test data are presented

Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin

Due to the globalization in the semiconductor supply chain, counterfeit dynamic random-access memory (DRAM) chips/modules have been spreading worldwide at an alarming rate. Deploying counterfeit DRAM modules into an electronic system can have severe consequences on security and reliability domains because of their sub-standard quality, poor performance, and shorter life span. Besides, studies suggest that a counterfeit DRAM can be more vulnerable to sophisticated attacks. However, detecting counterfeit DRAMs is very challenging because of their nature and ability to pass the initial testing. In this paper, we propose a technique to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM) to detect and prevent counterfeit DRAM modules. A silicon evaluation shows that the proposed method reliably identifies off-the-shelf DRAM modules from three major manufacturers