Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC

A Scan-Out Power Reduction Method for Multi-Cycle BIST

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops\u27 values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.2012 IEEE 21st Asian Test Symposium, 19-22 Nov. 2012, Niigata, Japa

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japa

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average)

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips

フィールドにおけるテスト印加と低電力論理BISTに関する研究

Advances in semiconductor process technology have resulted in various aging issues in field operation of Very Large Scale Integration (VLSI) circuits. For example, HCI (Hot carrier injection), BTI (Bias Temperature Instability), TDDB (Time Dependent Dielectric Breakdown) are well-known aging phenomena, and they can increase the circuit delay resulting in serious reliability problems. In order to avoid system failures caused by aging, recent design usually sets a certain timing margin in operational frequency of the circuit. However, it is difficult to determine the size of the proper timing margin because of the difficulty of prediction of its aging speed in actual use that is related to operational environment. Pessimistic prediction may result in performance sacrificing although it will improve the reliability of the system. BIST-based field test is a promising way to guarantee the reliability of the circuit through detecting the aging-induced faults during the circuit operation. However, the field test has a limitation on test application time, which makes it difficult to achieve high test quality. Therefore an effective test application method at field is required. In addition to the requirement of short test application time, the BIST-based field test requires performing at-speed testing in order to detect timing-related defects. However, it is well known that power dissipation during testing is much higher than that in normal circuit operation. Because excessive power dissipation causes higher IR-drop and higher temperature, it results in delay increase during testing, and in turn, causing false at-speed testing and yield loss. While many low power test methods have been proposed to tackle the test power issue, inadequate test power reduction and lower fault coverage still remain as important issues. Moreover, low power testing that just focuses on power reduction is insufficient. When the test power is reduced to a very low level, a timing-related defect may be missed by the test, and a defective circuit will appear to be a good part passing the test. Therefore, appropriate test power control is necessary though it was out of considering in the existing methods. In this dissertation, we first proposed a new test application to satisfy the limitation of short test application time for BIST-based field test, and then we proposed a new low power BIST scheme that focuses on controlling the test power to a specified value for improving the field test quality. In chapter 3, a new field test application method named “rotating test” is presented in which a set of generated test patterns to detect aging-induced faults is partitioned into several subsets, and apply each subset in one test session at field. In order to maximize the test quality for rotating test, we proposed test partitioning methods that refer to two items: First one aims at maximizing fault coverage of each subset obtained by partitioning. Second one aims at minimizing the detection time interval of all faults in rotating test to avoid system failures. Experimental results demonstrated the effectiveness of the proposed partitioning methods. In chapter 4, we proposed a new low power BIST scheme which can control the scan-in power, scan-out power and capture power while keeping test coverage at high level. In this scheme, a new circuit called pseudo low-pass filter (PLPF) is developed for scan-in power control, and a multi-cycle capture test technique is employed to reduce the capture power. In order to control scan-out power dissipated by test responses, we proposed a novel method that selects some flip-flops in scan chains at logic design phase, and fills the selected flip-flops with proper values before starting scan-shift operation so as to reduce the switching activity associated with scan-out. The experimental results for ISCAS-89 and ITC-99 benchmark circuits show that significant scan-in power reduction rate (the original rate of 50% is reduced to 7~8%) and capture power reduction rate (the original rate of 20% is reduced to 6~7%) were derived. With the scan-out controlling method, the scan-out power can be reduced from 17.2% to 8.4%, which could not be achieved by the conventional methods. Moreover, in order to control the test power to the specified rate to accommodate the various test power requirements. A scan-shift power controlling scheme was also discussed. It showed the capability of controlling any scan-shift toggle rate between 6.7% and 50%.九州工業大学博士学位論文 学位記番号:情工博甲第289号　学位授与年月日:平成26年3月25日1. INTRODUCTION|2. PRELIMINARY|3. BIST-BASED FIELD ROTATING TEST FOR AGING-INDUCED FAULT DETECTION|4. TEST POWER REDUCTION FOR LOGIC-BIST|5. SUMMARY九州工業大学平成25年

A Flexible Scan-in Power Control Method for Logic BIST

VLSIの微細化が進むと伴い，システムの大規模化・複雑化が進んでいる．また，システムテストやLSI出荷後のテスト(フィールドテスト)では，テストコストが増大する一方，厳しい制約下でテストを行う必要がある．例えば，少ないテストデータ量でかつチップ外部からの制御は少なくテストする必要があり，また，高品質なテストなために実際にユーザが使う回路のクロック速度でテストを行うことも求められる．これらの要求を満たすため，テスト容易化設計(Design For Testability：DFT)は不可欠であり，論理回路のフリップフロップ(Flip-Flop：FF)の値を直接観測・制御するスキャン設計は最も知られた手法である．更に，フィールドテストの厳しい制約を満すためLSIチップ上にテスタ機能を搭載してテストを行う，組込み自己テスト(Build-In Self-Test：BIST)が有効である．論理回路に対するBISTでは，よくスキャン設計を用いられる．簡単なLSI外部の制御でテストができ，また容易に実速度テストが行うことができるので，テストコスト削減やフィールドテスト等で有効である．しかし，スキャン設計を用いたBISTの問題点として，一般にテスト生成器が疑似ランダムに生成した高いトグル率(値が反転する確率50%)のテストパターンを使用するため，テストパターンをテスト対象回路に入力(スキャンイン動作)する際，多くのFFの値でトグルが発生し，通常の機能動作する時より消費電力が大きくなってしまう．消費電力が過度に増えると，回路内の発熱や電圧増減によるノイズ・遅延増減によって誤ったテスト結果をもたらすことになる．一方で，単純にテスト電力を下げることで低くなりすぎた場合，通常の機能動作では起きる故障が起こらなくなってしまい，不良の見逃しになる．したがって，回路毎に適切なテスト電力のレベルに合わせて，フレキシブルに電力を制御すべきである．また，テスト電力を制御する際，できるだけ制御回路の変更や面積オーバーヘッドが小さく，故障検出率に影響が少ない制御手法が良い．本論文では，フレキシブルなテスト電力を制御するために，テストパターンのトグル率を制御するスキャンイン電力制御手法を提案する．新たなスキャンイン電力低減回路(Phase Low Power Filter：PLPF)を用いたスキャンイン電力制御回路や制御手法を提案する．2章では，LSIテストの基礎となるスキャン設計やBISTの構造，テストの消費電力問題と対策について簡単に述べる．3章では，先行研究で提案したトグル率を低減する回路である従来のPLPFの説明を行い，動作や論理回路を最適化した新たなPLPFを提案した．提案したPLPFは，従来と同等なテストパターンのトグル率低減効果を実現し，論理回路の単純化と面積オーバーヘッドを削減できることを理論で説明した．4章では，フレキシブルなスキャンイン電力制御を行うための制御回路と制御手法について提案した．トグル率の低減レベルが異なるPLPFを複数用いて，スキャンシフト動作中に切り替えることでフレキシブルなスキャンイン電力を実現する．また，目標とするスキャンイン電力を達成するPLPFの切り替えるタイミングは多く存在するため，本論文では故障検出率と回路オーバーヘッドを考慮した3種類の制御手法(Basic，Swap，Moving)を提案した．5章では，10種類のベンチマーク回路に対して論理/故障シミュレーション結果と1つのベンチマーク回路で論理合成したときの面積結果を示した．論理シミュレーションでは，提案したPLPFのトグル率を測定し，従来のPLPFとほぼ同等なトグル率の低減効果を実現できることを確認した．そして，提案したスキャンイン電力制御手法は，目標スキャンイン電力(トグル率)より平均誤差±0.2%の精度で制御できることを示した．故障シミュレーションでは，単一縮退故障と遷移故障モデルを想定し，故障検出率を測定した．Moving制御手法で縮退故障検出率は平均8.41%，遷移故障検出率平均4.94%向上したことを示した．面積オーバーヘッド評価として，EDAツールを用いて制御回路を論理合成した時のセル数を算出した．その結果，従来のPLPFと提案したPLPFでは，約61%の面積を削減することができた．この章の結果より，提案したスキャンイン電力制御手法は，小面積オーバーヘッドで高い電力制御性と故障検出率の低下抑制効果を実現できることを示した．6章では，論理BISTにスキャンイン電力制御回路を搭載したCMOSのプロセスや対象回路規模が異なる2種類の試作チップを設計し，その測定結果を示した．試作チップの外部からBasic制御手法を用いてスキャンイン電力制御を行い，目標スキャンイン電力値と測定値である電流値・回路遅延に強い正負の相関を得ることができ，回路規模やプロセスの違いが有っても同様の結果が得られた．回路遅延は回路の発熱やテスト電力に大きく影響するため，回路遅延の制御ができていることは，電力制御ができていることを示し，この提案手法が誤ったテスト結果の回避に有効であることを示している．5章のシミュレーション結果と6章の試作チップ結果より，提案したスキャンイン電力制御手法の有効性の実証が示された．この提案手法を用いることで，フレキシブルなテスト電力制御かつ小面積オーバーヘッドで高信頼なテストの実現(特にフィールドテスト)，また，故障検出率低下抑制によるテスト時間短縮によってテストコスト削減の期待ができる．九州工業大学博士学位論文 学位記番号：情工博甲第333号 学位授与年月日：平成30年3月23日第1章 序論|第2章 高信頼なLSIテスト|第3章 スキャンイン電力低減|第4章 スキャンイン電力制御|第5章 シミュレーション評価|第6章 試作チップ評価 |第7章 結論九州工業大学平成29年