PROGRAMMABLE GENERATOR PRODUCING VIRTUAL ARBITRARY TEST PATTERNS

The suggested hybrid plan efficiently combines test compression with LBIST, where both techniques could work synergistically to provide top quality tests. It is composed of a straight line finite condition machine driving a suitable phase shifter, and it arrives with numerous features permitting this product to create binary sequences with preselected toggling (PRESTO) activity. We introduce a means to instantly select several controls from the generator offering simple and easy, precise tuning. This paper describes a minimal-power (LP) generator able to creating pseudorandom test designs with preferred toggling levels that has been enhanced fault coverage gradient in comparison using the best-to-date built-in self-test (BIST)-based pseudorandom test pattern machines. Exactly the same strategy is subsequently used to deterministically advice the generator toward test sequences with enhanced fault-coverage-to pattern-count ratios. In addition, this paper proposes an LP test compression way in which enables shaping the exam power envelope inside a fully foreseeable, accurate, and versatile fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. Experimental results acquired for industrial designs illustrate the practicality from the suggested test schemes and therefore are reported herein

AN INCLUSIVE TEST PATTERN GENERATOR USING DATA VOLUME COMPRESSION

Because the BIST power consumption can certainly exceed the utmost ratings when testing as fast as possible, scan patterns should be shifted in a programmable low speed, and just the final couple of cycles and also the capture cycle are applied at its peak frequency. Within this paper, we advise a PRPG for LP BIST applications. The suggested hybrid solution enables someone to efficiently combine test compression with logic BIST, where both techniques could work synergistically to provide top quality test. Therefore, it is a really attractive LP test plan that enables for buying and selling-off test coverage, pattern counts, and toggling rates in an exceedingly flexible manner. Particularly, several hybrid BIST schemes store deterministic top-up patterns around the tester inside a compressed form, after which make use of the existing BIST hardware to decompress these test patterns. The bottom is thus provided by  observe that chain 45 isn't incorporated because it features just one specified scan cell. A high probability of manufacturing confirmed logic value inside a purely pseudorandom fashion is really a rationale behind excluding from the base scan chains hosting just one specified bit. Just like conventional scan-based test, hybrid schemes, because of the high data activity connected with scan-based test operations, may consume a lot more power than the usual circuit under-test is built to function under. The generator mainly is aimed at lowering the switching activity during scan loading because of its preselected toggling (PRESTO) levels. LP PRPG can also be able to serving as a completely functional test data decompress or having the ability to control scan shift-in switching activity through the entire process of encoding

A RANDOM TEST PATTERN GENERATOR WITH ENHANCED FAULT COVERAGE

Particularly, several hybrid BIST schemes store deterministic top-up patterns around the tester inside a compressed form, after which make use of the existing BIST hardware to decompress these test patterns. Just like conventional scan-based test, hybrid schemes, because of the high data activity connected with scan-based test operations, may consume a lot more power than the usual circuit under-test is built to function under. Because the BIST power consumption can certainly exceed the utmost ratings when testing as fast as possible, scan patterns should be shifted in a programmable low speed, and just the final couple of cycles and also the capture cycle are applied at its peak frequency. Within this paper, we advise a PRPG for LP BIST applications. The suggested hybrid solution enables someone to efficiently combine test compression with logic BIST, where both techniques could work synergistically to provide top quality test. Therefore, it is a really attractive LP test plan that enables for buying and selling-off test coverage, pattern counts, and toggling rates in an exceedingly flexible manner. The generator mainly is aimed at lowering the switching activity during scan loading because of its preselected toggling (PRESTO) levels. LP PRPG can also be able to serving as a completely functional test data decompress or having the ability to control scan shift-in switching activity through the entire process of encoding. The bottom is thus provided by  observe that chain 45 isn't incorporated because it features just one specified scan cell. A high probability of manufacturing confirmed logic value inside a purely pseudorandom fashion is really a rationale behind excluding from the base scan chains hosting just one specified bit

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japa

A Scan-Out Power Reduction Method for Multi-Cycle BIST

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops\u27 values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.2012 IEEE 21st Asian Test Symposium, 19-22 Nov. 2012, Niigata, Japa

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average)

Rotorcraft digital advanced avionics system (RODAAS) functional description

A functional design of a rotorcraft digital advanced avionics system (RODAAS) to transfer the technology developed for general aviation in the Demonstration Advanced Avionics System (DAAS) program to rotorcraft operation was undertaken. The objective was to develop an integrated avionics system design that enhances rotorcraft single pilot IFR operations without increasing the required pilot training/experience by exploiting advanced technology in computers, busing, displays and integrated systems design. A key element of the avionics system is the functionally distributed architecture that has the potential for high reliability with low weight, power and cost. A functional description of the RODAAS hardware and software functions is presented

Staffed NextGen Tower Human-in-the-Loop 2 (SNT HITL 2): Camera Integration Evaluation

Objective: The purpose of this study is to investigate the effect of a Staffed NextGen Tower (SNT) environment on air traffic control (ATC) operations. The primary objective was to determine whether cameras are beneficial for SNT operations. Background: The SNT concept shifts from relying primarily on the out-the-window view to a model that relies more on using surveillance and cameras. There are different ways to implement the SNT concept. Two alternatives are Supplemental use (in addition to out the window display) and Contingency use (when the out the window view is unavailable). Method: Eight controllers ran traffic in this study with two main conditions, Supplemental and Contingency, with four off-nominal events (aircraft crosses unoccupied runway, aircraft crosses occupied runway, wheels up on approach, aborted takeoff aircraft on runway). Results: The controllers were able to perform their jobs effectively in both Supplemental and Contingency conditions using cameras and surveillance displays. Controllers in conditions with the camera consistently detected the \u2015wheels up on approach\u2016 off-nominal condition. Controllers in conditions without the camera did not detect the \u2015wheels up on approach\u2016 off-nominal condition at all. The other three off-nominal conditions were detected primarily using the Traffic Information Display System (TIDS) and alerts. The controllers rated the camera as essential in both Supplemental and Contingency conditions, although less for Supplemental than Contingency. Controllers agreed that the SNT concept would be beneficial for the National Airspace System (NAS) and for control tower operations. Conclusion: Results of this study show that controllers can perform their jobs effectively in both Supplemental and Contingency SNT environments and show that cameras provide a benefit to operations. Applications: These findings will directly influence decisions on the SNT concept implementation. Although cameras were found to be beneficial, we will still need to refine the details of camera coverage, display configuration, and control functionality. We believe that small improvements based on controller feedback from this study should lead to enhanced situational awareness for controllers and improved ATC performance