Design for testability of a latch-based design

Abstract. The purpose of this thesis was to decrease the area of digital logic in a power management integrated circuit (PMIC), by replacing selected flip-flops with latches. The thesis consists of a theory part, that provides background theory for the thesis, and a practical part, that presents a latch register design and design for testability (DFT) method for achieving an acceptable level of manufacturing fault coverage for it. The total area was decreased by replacing flip-flops of read-write and one-time programmable registers with latches. One set of negative level active primary latches were shared with all the positive level active latch registers in the same register bank. Clock gating was used to select which latch register the write data was loaded to from the primary latches. The latches were made transparent during the shift operation of partial scan testing. The observability of the latch register clock gating logic was improved by leaving the first bit of each latch register as a flip-flop. The controllability was improved by inserting control points. The latch register design, developed in this thesis, resulted in a total area decrease of 5% and a register bank area decrease of 15% compared to a flip-flop-based reference design. The latch register design manages to maintain the same stuck-at fault coverage as the reference design.Salpaperäisen piirin testattavuuden suunnittelu. Tiivistelmä. Tämän opinnäytetyön tarkoituksena oli pienentää digitaalisen logiikan pinta-alaa integroidussa tehonhallintapiirissä, korvaamalla valitut kiikut salpapiireillä. Opinnäytetyö koostuu teoriaosasta, joka antaa taustatietoa opinnäytetyölle, ja käytännön osuudesta, jossa esitellään salparekisteripiiri ja testattavuussuunnittelun menetelmä, jolla saavutettiin riittävän hyvä virhekattavuus salparekisteripiirille. Kokonaispinta-alaa pienennettiin korvaamalla luku-kirjoitusrekistereiden ja kerran ohjelmoitavien rekistereiden kiikut salpapiireillä. Yhdet negatiivisella tasolla aktiiviset isäntä-salpapiirit jaettiin kaikkien samassa rekisteripankissa olevien positiivisella tasolla aktiivisten salparekistereiden kanssa. Kellon portittamisella valittiin mihin salparekisteriin kirjoitusdata ladattiin yhteisistä isäntä-salpapireistä. Osittaisessa testipolkuihin perustuvassa testauksessa salpapiirit tehtiin läpinäkyviksi siirtooperaation aikana. Salparekisterin kellon portituslogiikan havaittavuutta parannettiin jättämällä jokaisen salparekisterin ensimmäinen bitti kiikuksi. Ohjattavuutta parannettiin lisäämällä ohjauspisteitä. Salparekisteripiiri, joka suunniteltiin tässä diplomityössä, pienensi kokonaispinta-alaa 5 % ja rekisteripankin pinta-alaa 15 % verrattuna kiikkuperäiseen vertailupiiriin. Salparekisteripiiri onnistuu pitämään saman juuttumisvikamallin virhekattavuuden kuin vertailupiiri

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

This paper presents UA2TPG, a static analysis tool for the untestability proof and automatic test pattern generation for SEUs in the configuration memory of SRAM-based FPGA systems. The tool is based on the model-checking verification technique. An accurate fault model for both logic components and routing structures is adopted. Experimental results show that many circuits have a significant number of untestable faults, and their detection enables more efficient test pattern generation and on-line testing. The tool is mainly intended to support on-line testing of critical components in FPGA fault-tolerant systems

Design of On-Chip Self-Testing Signature Register

Over the last few years, scan test has turn out to be too expensive to implement for industry standard designs due to increasing test data volume and test time. The test cost of a chip is mainly governed by the resource utilization of Automatic Test Equipment (ATE). Also, it directly depends upon test time that includes time required to load test program, to apply test vectors and to analyze generated test response of the chip. An issue of test time and data volume is increasingly appealing designers to use on-chip test data compactors, either on input side or output side or both. Such techniques significantly address the former issues but have little hold over increasing number of input-outputs under test mode. Further, test pins on DUT are increasing over the generations. Thus, scan channels on test floor are falling short in number for placement of such ICs. To address issues discussed above, we introduce an on-chip self-testing signature register. It comprises a response compactor and a comparator. The compactor compacts large chunk of response data to a small test signature whereas the comparator compares this test signature with desired one. The overall test result for the design is generated on single output pin. Being no storage of test response is demanded, the considerable reduction in ATE memory can be observed. Also, with only single pin to be monitored for test result, the number of tester channels and compare edges on ATE side significantly reduce at the end of the test. This cuts down maintenance and usage cost of test floor and increases its life time. Furthermore reduction in test pins gives scope for DFT engineers to increase number of scan chains so as to further reduce test time

Seismic events miss important kinematically governed grain scale mechanisms during shear failure of porous rock

Catastrophic failure in brittle, porous materials initiates when smaller-scale fractures localise along an emergent fault zone in a transition from stable crack growth to dynamic rupture. Due to the rapid nature of this critical transition, the precise micro-mechanisms involved are poorly understood and difficult to image directly. Here, we observe these micro-mechanisms directly by controlling the microcracking rate to slow down the transition in a unique rock deformation experiment that combines acoustic monitoring (sound) with contemporaneous in-situ x-ray imaging (vision) of the microstructure. We find seismic amplitude is not always correlated with local imaged strain; large local strain often occurs with small acoustic emissions, and vice versa. Local strain is predominantly aseismic, explained in part by grain/crack rotation along an emergent shear zone, and the shear fracture energy calculated from local dilation and shear strain on the fault is half of that inferred from the bulk deformation

A multi-physics visco-plasticity theory for porous sedimentary rocks

In this thesis a physics-based constitutive theory for sedimentary porous rocks is proposed combining the results of laboratory tests, theoretical analysis, and numerical validation. The motivation for this framework stems from triaxial experiments on calcarenite performed up to 50% axial strain inside an X-Ray CT-scan. These tests revealed that: 1) calcarenite plastified at the first increment of displacement; 2) with increasing axial strain, the material underwent a phase change where all the inter-granular bonds broke, the pore space collapsed and the material behaved as sand; 3) in repeating loading-unloading cycles and relaxation tests, the deformation of the rock became increasingly more rate-dependent with strain, as a result of the aforementioned phase change and reorganization of released grains. Motivated by these experiments, a visco-plastic flow law is proposed. The viscosity of the material is assumed to be a function of the temperature, pore-pressure and energy required to alter the inter-granular interfaces. Thus, stress equilibrium and flow law are fully coupled to the energy and mass conservation laws, constituting a closed system of equations. In order to solve this system, the theoretical framework is implemented into the tightly coupled Finite Element code REDBACK, and its qualitative behaviour is analysed in monotonous and cyclic isotropic compression as well as in direct shear for different loading rates. A series of numerical calibration tests against different types of rocks (sandstone, mudstone, calcarenite), saturating conditions (dry, wet) and stress paths (triaxial, isotropic) is then performed, concluding that the mechanical response of sedimentary porous rocks in strains usually achieved in laboratory testing is determined by the strength of the cementitious material bonding the grains. The latter is shown to be stress path dependent under the hypotheses made in this thesis and the interfaces are shown to obey a Kelvin-like law at the microscopic level. Finally, the proposed framework is applied at geophysical scale problem and is qualitatively linked with theoretical studies of landslide and faults in the literature. A reinterpretation of the brittle to ductile transition is then attempted linking the two cases (brittle and ductile) to the types of instabilities that the model theoretically predicts

High Quality Compact Delay Test Generation

Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test

Secure Split Test for Preventing IC Piracy by Un-Trusted Foundry and Assembly

In the era of globalization, integrated circuit design and manufacturing is spread across different continents. This has posed several hardware intrinsic security issues. The issues are related to overproduction of chips without knowledge of designer or OEM, insertion of hardware Trojans at design and fabrication phase, faulty chips getting into markets from test centers, etc. In this thesis work, we have addressed the problem of counterfeit IC‟s getting into the market through test centers. The problem of counterfeit IC has different dimensions. Each problem related to counterfeiting has different solutions. Overbuilding of chips at overseas foundry can be addressed using passive or active metering. The solution to avoid faulty chips getting into open markets from overseas test centers is secure split test (SST). The further improvement to SST is also proposed by other researchers and is known as Connecticut Secure Split Test (CSST). In this work, we focus on improvements to CSST techniques in terms of security, test time and area. In this direction, we have designed all the required sub-blocks required for CSST architecture, namely, RSA, TRNG, Scrambler block, study of benchmark circuits like S38417, adding scan chains to benchmarks is done. Further, as a security measure, we add, XOR gate at the output of the scan chains to obfuscate the signal coming out of the scan chains. Further, we have improved the security of the design by using the PUF circuit instead of TRNG and avoid the use of the memory circuits. This use of PUF not only eliminates the use of memory circuits, but also it provides the way for functional testing also. We have carried out the hamming distance analysis for introduced security measure and results show that security design is reasonably good.Further, as a future work we can focus on: • Developing the circuit which is secuered for the whole semiconductor supply chain with reasonable hamming distance and less area overhead

Submarine mass wasting processes along the continental slope of the Middle American Trench

This Thesis work presents a regional-scale study of submarine mass-wasting phenomena of the continental slope of a subduction zone. The nature of the study makes it a new, outstanding contribution for two main reasons: 1) The large-scale and interdisciplinary characters of the study conform a comprehensive investigation - unmatched by any other previous study- of land sliding processes along the slope of a tectonically-active convergent margin. 2) The investigation is also unique because it looks into the processes at a subduction zone dominated by tectonic erosion. This type of geological setting represents about 50% of the world subduction zone systems, but it has been overlooked in previous studies of mass wasting processes. The study region is located along a segment of the Middle America Trench (MAT) that extends about 1500 km from the Costa Rica - Panama border to the Guatemala - Mexico boundary. The study investigates the structures of the continental slope of the Pacific-Ocean-side of Central America and the trench-region of the incoming oceanic Cocos plate. We have investigated the distribution of submarine slope failures and their deposits, the type of failures, and their seafloor morphology. We have also investigated possible preconditioning and triggering mechanisms, and the relationship of those mechanisms and the variability in failure type to the tectonic processes of this particular geological setting. Finally, we have made some inferences of the significance of mass wasting processes in the long-term evolution of the slope, compared to other geological settings. The Central America subduction zone has been the locus of intense, continued geoscientific investigation since the late 1970s that culminated with the selection of the region as the focus site for the US-Margins program and the German SFB574 during the first decade of the 21st century. Those two programs included research in a broad range of topics that attempted to advance our understanding of the entire subduction zone system. As a result numerous projects from both communities have benefited from close collaborations. This PhD work is integrated within the research project SFB 574, financed by the DFG, that has as main research goal investigations on “Volatiles and fluids in subduction zones and their impact on climate feedback and trigger mechanisms for natural disasters”. We have analyzed a database containing a compilation of multibeam bathymetry of 7 research cruises, 3 cruises of side-scan sonar imagery and core samples of a dedicated cruise. The database has been assembled in a collaborative effort between both USMargins and SFB 574 communities. Based on seafloor morphology and backscatter imagery, and seismic images we have mapped and classified 147 submarine slope failures in the region. Slope failures vary in their type, abundance and distribution along and across the slope to define six distinct segments along the MAT. The lateral extent of the six segments correlates well with similar along-trench segmentation in the character of the incoming ocean plate, expressed as changes in its relief, age and crustal thickness. We have also found that the six along-margin segments display changes in the across-slope structuring of the different geological elements, including changes in the morphological expression of upper, middle and lower slope, total slope width, and slope dip angle. This structuring of the elements of the slope appears to be related to a longterm evolution caused by the tectonic processes associated to subduction erosion. One segment covers the area of under-thrusting of Cocos Ridge under the shelf-slope offshore Osa Peninsula (southern Costa Rica). Here, 1-km-high narrow, sharp ridges and small conical seamounts festooning Cocos Ridge cause slumps often with rock and debris avalanches from a short, steep continental slope. A second segment occurs offshore central Costa Rica, where large conical seamounts and ridges of 1-3 km high and 40 km wide under-thrust the continental slope causing large re-entries of the slope toe, and furrows across the slope formed by collapse, of previously uplifted upper plate, along steep headwalls behind the under-thrusting seamounts. Failures have generated large slumps, debris flows and rock avalanches containing blocks up to 500 m in diameter. In contrast at a third segment in northern Costa Rica, offshore the North Nicoya Peninsula, a smooth incoming plate is parallel opposite by a continental slope lacking relevant mass wasting structures. The contiguous fourth segment offshore Nicaragua displays a steep middle slope with large translational slides opposite an ocean plate with numerous 1-km-tall seamounts and 100s-meter-high horst and graben relief. Under the fifth segment, offshore El Salvador, subducts a well developed horst and graben relief, but somewhat surprising the segment displays a generally failure-free slope, and only the uppermost slope displays a series of small translation slides The plate under-thrusting the sixth segment offshore Guatemala is similarly characterized by a horst and graben terrain. However, here a steeper slope exhibits frequent, small-scale failures, a few km wide, across the entire segment