High Quality Test Generation Targeting Power Supply Noise

Delay test is an essential structural manufacturing test used to determine the maximal frequency at which a chip can run without incurring any functional failures. The central unsolved challenge is achieving high delay correlation with the functional test, which is dominated by power supply noise (PSN). Differences in PSN between functional and structural tests can lead to differences in chip operating frequencies of 30% or more. Pseudo functional test (PFT), based on a multiple-cycle clocking scheme, has better PSN correlation with functional test compared with traditional two-cycle at-speed test. However, PFT is vulnerable to under-testing when applied to delay test. This work aims to generate high quality PFT patterns, achieving high PSN correlation with functional test. First, a simulation-based don’t-care filling algorithm, Bit-Flip, is proposed to improve the PSN for PFT. It relies on randomly flipping a group of bits in the test pattern to explore the search space and find patterns that stress the circuits with the worst-case, but close to functional PSN. Experimental results on un-compacted patterns show Bit-Flip is able to improve PSN as much as 38.7% compared with the best random fill. Second, techniques are developed to improve the efficiency of Bit-Flip. A set of partial patterns, which sensitize transitions on critical cells, are pre-computed and later used to guide the selection of bits to flip. Combining random and deterministic flipping, we achieve similar PSN control as Bit-Flip but with much less simulation time. Third, we address the problem of automatic test pattern generation for extracting circuit timing sensitivity to power supply noise during post-silicon validation. A layout-aware path selection algorithm selects long paths to fully span the power delivery network. The selected patterns are intelligently filled to bring the PSN to a desired level. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high. Finally, the impacts of compression on power supply noise control are studied. Illinois Scan and embedded deterministic test (EDT) patterns are generated. Then Bit-Flip is extended to incorporate the compression constraints and applied to compressible patterns. The experimental results show that EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Stress Monitoring of Post-processed MEMS Silicon Microbridge Structures Using Raman Spectroscopy

Inherent residual stresses during material deposition can have profound effects on the functionality and reliability of fabricated Micro-Electro-Mechanical Systems (MEMS) devices. Residual stress often causes device failure due to curling, buckling, or fracture. Typically, the material properties of thin films used in surface micromachining are not well controlled during deposition. The residual stress; for example, tends to vary significantly for different deposition methods. Currently, few nondestructive techniques are available to measure residual stress in MEMS devices prior to the final release etch. In this research, micro-Raman spectroscopy is used to measure the residual stresses in polysilicon MEMS microbridge devices. This measurement technique was selected since it is nondestructive, fast, and provides the potential for in-situ stress monitoring. Raman spectroscopy residual stress profiles on unreleased and released MEMS microbridge beams are compared to analytical and FEM models to assess the viability of micro-Raman spectroscopy as an in-situ stress measurement technique. Raman spectroscopy was used during post-processing phosphorus ion implants on unreleased MEMS devices to investigate and monitor residual stress levels at key points during the post-processing sequences. As observed through Raman stress profiles and verified using on-chip test structures, the post-processing implants and accompanying anneals resulted in residual stress relaxation of over 90%

Towards Structural Testing of Superconductor Electronics

Many of the semiconductor technologies are already\ud facing limitations while new-generation data and\ud telecommunication systems are implemented. Although in\ud its infancy, superconductor electronics (SCE) is capable of\ud handling some of these high-end tasks. We have started a\ud defect-oriented test methodology for SCE, so that reliable\ud systems can be implemented in this technology. In this\ud paper, the details of the study on the Rapid Single-Flux\ud Quantum (RSFQ) process are presented. We present\ud common defects in the SCE processes and corresponding\ud test methodologies to detect them. The (measurement)\ud results prove that we are able to detect possible random\ud defects for statistical purposes in yield analysis. This\ud paper also presents possible test methodologies for RSFQ\ud circuits based on defect oriented testing (DOT)

Chatter, process damping, and chip segmentation in turning: A signal processing approach

An increasing number of aerospace components are manufactured from titanium and nickel alloys that are difficult to machine due to their thermal and mechanical properties. This limits the metal removal rates that can be achieved from the production process. However, under these machining conditions the phenomenon of process damping can be exploited to help avoid self-excited vibrations known as regenerative chatter. This means that greater widths of cut can be taken so as to increase the metal removal rate, and hence offset the cutting speed restrictions that are imposed by the thermo-mechanical properties of the material. However, there is little or no consensus as to the underlying mechanisms that cause process damping. The present study investigates two process damping mechanisms that have previously been proposed in the machining literature: the tool flank/workpiece interference effect, and the short regenerative effect. A signal processing procedure is employed to identify flank/workpiece interference from experimental data. Meanwhile, the short regenerative model is solved using a new frequency domain approach that yields additional insight into its stabilising effect. However, analysis and signal processing of the experimentally obtained data reveals that neither of these models can fully explain the increases in stability that are observed in practice. Meanwhile, chip segmentation effects were observed in a number of measurements, and it is suggested that segmentation could play an important role in the process-damped chatter stability of these materials

cis-regulatory circuits regulating NEK6 kinase overexpression in transformed B cells Are super-enhancer independent

Alterations in distal regulatory elements that control gene expression underlie many diseases, including cancer. Epigenomic analyses of normal and diseased cells have produced correlative predictions for connections between dysregulated enhancers and target genes involved in pathogenesis. However, with few exceptions, these predicted cis-regulatory circuits remain untested. Here, we dissect cis-regulatory circuits that lead to overexpression of NEK6, a mitosis-associated kinase, in human B cell lymphoma. We find that only a minor subset of predicted enhancers is required for NEK6 expression. Indeed, an annotated super-enhancer is dispensable for NEK6 overexpression and for maintaining the architecture of a B cell-specific regulatory hub. A CTCF cluster serves as a chromatin and architectural boundary to block communication of the NEK6 regulatory hub with neighboring genes. Our findings emphasize that validation of predicted cis-regulatory circuits and super-enhancers is needed to prioritize transcriptional control elements as therapeutic targets

Generation and sampling of quantum states of light in a silicon chip

Implementing large instances of quantum algorithms requires the processing of many quantum information carriers in a hardware platform that supports the integration of different components. While established semiconductor fabrication processes can integrate many photonic components, the generation and algorithmic processing of many photons has been a bottleneck in integrated photonics. Here we report the on-chip generation and processing of quantum states of light with up to eight photons in quantum sampling algorithms. Switching between different optical pumping regimes, we implement the Scattershot, Gaussian and standard boson sampling protocols in the same silicon chip, which integrates linear and nonlinear photonic circuitry. We use these results to benchmark a quantum algorithm for calculating molecular vibronic spectra. Our techniques can be readily scaled for the on-chip implementation of specialised quantum algorithms with tens of photons, pointing the way to efficiency advantages over conventional computers

On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approac