Optimal Geometry of CMOS Voltage-Mode and Current-Mode Vertical Magnetic Hall Sensors

Four different geometries of a vertical Hall sensor are presented and studied in this paper. The current spinning technique compensates for the offset and the sensors, driven in current-mode, provide a differential signal current for a possible capacitive integration over a defined time-slot. The sensors have been fabricated using a 6-metal 0.18-μm CMOS technology and fully experimentally tested. The optimal solution will be further investigated for bendable electronics. Measurement results of the four structures over the 10 available samples show for the best geometry an offset of 41.66 ± 8 μT and a current-mode sensitivity of 9 ± 0.1 %/T. Since the figures widely change with geometry, a proper choice secures optimal performance

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Optical Synoptic Telescopes: New Science Frontiers

Over the past decade, sky surveys such as the Sloan Digital Sky Survey have proven the power of large data sets for answering fundamental astrophysical questions. This observational progress, based on a synergy of advances in telescope construction, detectors, and information technology, has had a dramatic impact on nearly all fields of astronomy, and areas of fundamental physics. The next-generation instruments, and the surveys that will be made with them, will maintain this revolutionary progress. The hardware and computational technical challenges and the exciting science opportunities are attracting scientists and engineers from astronomy, optics, low-light-level detectors, high-energy physics, statistics, and computer science. The history of astronomy has taught us repeatedly that there are surprises whenever we view the sky in a new way. This will be particularly true of discoveries emerging from a new generation of sky surveys. Imaging data from large ground-based active optics telescopes with sufficient etendue can address many scientific missions simultaneously. These new investigations will rely on the statistical precision obtainable with billions of objects. For the first time, the full sky will be surveyed deep and fast, opening a new window on a universe of faint moving and distant exploding objects as well as unraveling the mystery of dark energy.Comment: 12 pages, 7 figure

Frequency Constraints on D.C. Biasing in Deep Submicron Technologies

The progression of technology has required smaller devices to achieve faster circuits and more power-efficient systems. However, with supply voltage and device intrinsic gain decreasing, device biasing in deep sub-micron technologies can be challenging. A low-voltage current source is analyzed in a 28 nm CMOS, 0.85 V supply, technology to take into account undesirable effects introduced by aggressively scaled technologies. The analysis includes intrinsic gain degradation as well as short-channel effects to create a more accurate design methodology. Amplifier design challenges in deep sub-micron technologies are discussed along with a DAC bias correction technique. Frequency dependence of output resistance for a simple and a proposed current source is presented. For the proposed current source the frequency dependence of output resistance was found to be dictated by the frequency response of the amplifier. To demonstrate the relevance of current source resistance bandwidth a common-mode logic circuit is considered, and fabrication plans are discussed along with future work

A compact aVLSI conductance-based silicon neuron

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neuromorphic systems. The aVLSI neuron consists of a soma (cell body) and a single synapse, which is capable of linearly summing both the excitatory and inhibitory postsynaptic potentials (EPSP and IPSP) generated by the spikes arriving from different sources. Rather than biasing the silicon neuron with different parameters for different spiking patterns, as is typically done, we provide digital control signals, generated by an FPGA, to the silicon neuron to obtain different spiking behaviours. The proposed neuron is only ~26.5 um2 in the IBM 130nm process and thus can be integrated at very high density. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons.Comment: BioCAS-201

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Yield improvement using configurable analogue transistors (CATs)

Continued process scaling has led to significant yield and reliability challenges for today’s designers. Analogue circuits are particularly susceptible to poor variation, driving the need for new yield resilient techniques in this area. This paper describes a new configurable analogue transistor structure and supporting methodology that facilitates variation compensation at the post-manufacture stage. The approach has demonstrated significant yield improvements and can be applied to any analogue circui