High-freequency CMOS VLSI chip testability and on-chip interconnect modeling

As high-speed digital and radio-frequency mixed-signal integrated circuits become increasingly common in product designs in industry, it is important for VLSI designers to be familiar with the challenges of chip testing and the behavior of circuit elements, including on-chip interconnect, at high frequencies. Expensive, specialized test equipment and software simulation packages for high-frequency chip testing and design are not always accessible for student research. This thesis documents the setup and characterization of a best-possible environment for high-frequency chip testing and data acquisition using existing laboratory equipment and resources. Experimental methodologies and measurement results of on-chip interconnect signal integrity and delay, ring oscillator noise and timing jitter, and time-domain reflectometry (TDR) testing are presented. Methods of modeling on-chip interconnect at high frequencies using field solvers and equivalent circuits are discussed. Lastly, the designs of single-ended and differential ring oscillators, for use in future voltage-controlled oscillator (VCO) and phase-locked loop (PLL) test chip designs, are presented and analyzed

An automated N-port network analyzer for linear and non linear multi-port RF and digital circuits

A new automated N-port time and frequency domain network analyzer based on the microwave transition analyzer MTA, used as a high speed digital oscilloscope, has been developed. The validity of the developed system is demonstrated with number of experimental measurements on different multi-ports structures

Investigations on electromagnetic noises and interactions in electronic architectures : a tutorial case on a mobile system

Electromagnetic interactions become critic in embedded and smart electronic structures. The increase of electronic performances confined in a finite volume or support for mobile applications defines new electromagnetic environment and compatibility configurations (EMC). With canonical demonstrators developed for tutorials and EMC experiences, this paper present basic principles and experimental techniques to investigate and control these severe interferences. Some issues are reviewed to present actual and future scientific challenges for EMC at electronic circuit level

A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed

Parametric Macromodels of Differential Drivers and Receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link

Behavioral modeling of digital IC input and output ports

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to the characterization of actual device

A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements

A description is given of a test structure consisting of a combination of a ring oscillator and an inverter chain. The circuit can be used to carry out propagation delay measurements on two circuit types and under a number of load conditions. Full characterization only takes one test circuit. The elements of this structure are connected to a programmable load varying from a fan-in of 1 up to a fan-in of 15. In this way, the operating environment of the circuit can be simulated in hardware. The measurements can be carried out by means of a conventional automated digital measurement system providing AC and DC parametric measurement capabilities