A description is given of a test structure consisting of a combination of a ring oscillator and an inverter chain. The circuit can be used to carry out propagation delay measurements on two circuit types and under a number of load conditions. Full characterization only takes one test circuit. The elements of this structure are connected to a programmable load varying from a fan-in of 1 up to a fan-in of 15. In this way, the operating environment of the circuit can be simulated in hardware. The measurements can be carried out by means of a conventional automated digital measurement system providing AC and DC parametric measurement capabilities

Kerkhoff, H.

Kloppers, G.

Lippe, K.

Morskieft, N.

English

Kerkhoff, Hans G.

University of Twente Research Information

Proc. IEEE 1989 Int. Conference on Microelectronic Test Structures, Vol2, No. 1, March 1989 225 A PROGRAMMABLE-LOAD CMOS RING OSCILLATOR/ INVERTER CHAIN FOR PROPAGATION-DELAY MEASUREMENTS K. Lippe, H'. Kerkhoff, G. Kloppers and N .  Morskieft University of Twente IC- Technology and Electronics Group P.O. Box 217 7500 AE Enschede The Netherlands Abstract This paper describes a test structure con- sisting of a ring oscillator and an inverter chain. The load of the elements of the ring oscillator and the inverter chain is programmable. The propagation- delay times measured give a better correlation with real logic circuits. Introduction A test structure often used for the charac- terization of the circuit performance,in a particular process is the ring oscillator C l 1  or the inverter chain C21. Characterization involves the evaluation of parameters such as speed/power product, propagation- delay time and fan-out capability. and inverter chains have been reported. Generally, inverters or NOR gates [31 have been used to built these structures. Ring oscillators and inverter chains are often built with elements having a fan-out or fan- in of 1 .  The propagation-delay time or oscillation frequency of such structures therefore provides an optimistic prediction of the propagation-delay times measured under real load conditions. This is because effects due to interconnect capacitances and actual circuit loads are not taken into account. Propagation- delay times measured from such structures can there- fore only serve as an upper bound for delays that can be expected for the actual logic circuits. Yu et al. C41 found propagation-delay times in a high speed ring oscillator that varied from 100 ps up to 2 n s . ,  depending upon the load. Several types of ring oscillator circuits having various fixed loads were used for their measurements. Several implementations of ring oscillators This paper presents a test structure consist- ing of a combination of a ring oscillator and an inverter chain. The elements of this structure are connected to a programmable load varying from a fan-in of 1 upto a fan-in of 15. In this way, the operating environment of the circuit can be simulated in hard- ware. The measurements can be carried out by means of a conventional automated digital measurement system providing AC- and DC-parametric measurement capabili- ties. Circuit description The circuit diagram of the test structure is shown in figure 1 .  A single delay element is denoted as T. If the input RO-enable is HIGH, the circuit acts as a ring oscillator; if the input RO-enable is LOW, the circuit acts as an inverter chain. Two transmission gates are used to select the mode of  operation. The circuit consists of 43 delay-elements in the ring oscillator mode. The number of delay elements is chosen in such a way that the measurements can be carried out with sufficient accuracy. The input Trigger is used as the start input of the ring oscillator in order to synchronize the ring oscillator and avoid oscillation at a high harmonic frequency. The oscilla- tion frequencv can be measured at output RO-out. chain consists of 43 delay-elements. If a transition In the inverter-chain mode the inverter Fig. I .  Circuit diagram of the ring oscillator/ inverter chain. from LOW to HIGH is applied to the input Trigger, a pulse with width w can be measured at the output IC-out. The second input of the first delay element of the inverter chain is connected to HIGH in order to obtain an equal delay path in both ring-oscilla'3r mode and the inverter-chain mode. Figure 2 shows the circuit diagram of a single delay element. Transmission gates are used for the selection of the appropriate load. The load of the delay element can be programmed by means of the inputs se12, se14 and se18. The loads LD2, LD4 and LD8 consist respectively of 2, 4 or 8 inverters in parallel. The chip lay-out of the delay element is shown in figure 4. ..I8 ,f'L 1  I 0 out Fig. 2 .  Circuit diagram of a delay element 7 .  Simulation results The SPICE simulations of the test structure in the ring-oscillator mode and the inverter-chain mode showed a linear relationship between the propa- gation delay times and the load of each delay element. The parasitic effects due to the transmission gates were taken into account. The simulation results are depicted in figure 3. CH2693-0/89/0000-225$01 .00"1989 IEEE I 226 ROC. IEEE 1989 Int. Conference on Microelectronic Test Structures, Vol 2, No. 1, March 1989 . Fig. 3. Propagation-delay versus load for the inverter chain. The test circuit is part of a CMOS Process Control Module (PCM) and incorporates test structures for the evaluation of process-parameters, SPICE-mosfet model-parameters and circuit-parameters. A 2 X N  probe pad arrangement is used 161. The PCM has been fabricated at the university of Twente in the Retrograde Twin Well UT-CMOS process C71. Fig. 4. Chip lay-out of a delay element. Conclusions Traditional designs of ring oscillators and inverter chains are often built up with single delay elements, e.g. inverters or NOR gates. The propagation delay times found, only serve as an upper bound for'the actual logic circuits. For a better correlation with real logic circuits the measurements have to be carried out on several test structures, having different load conditions. The circuit presented here offers the capability to carry out propagation delay-measurements on two circuit tvDes and under a number of load conditions. Its one 1 1 1  121 131 141 C5l 161 171 _.  feature is that full characterization only takes test circuit. References R. Dennard et a l . ,  " 1  um MOSFET VLSI technoloey: part 11-Device design and characteristics for high performance logic applications", IEEE .I. Solid-. State Circuits, SC-14, pp. 247-254, Apr. 1979. D.J. Radack and L.W. Linholm, "The Application pf Microelectronic Test Structures For Propagation Delay Measurements", IEEE Workshop On Test Structures, pp. 190-209, Feb. 1986. W.E. Ham, "Comprehensive Test Pattern and Approach .~ for characterizing SOS Technology", National Bureau of Standards Special Publ. 400-56, Jan. 1980. H. Yu et al., " 1  um MOSFET VLSI Technology: part I -An overview", IEEE J. Solid-state Circuits, SC-14, pp. 280-283, Feb. 1982. N. Nasaki, "Higher harmonic generation in CMOS/SOS ring oscillators", IEEE Trans. Electron Devices, vol. ED-29, pp. 280-283, Feb. 1982. M.G. Buehler, "Comprehensive testpatterns with modular teststructures: The 2 by N probe pad array approach.", Solid State Technology, vol. 22, no. I O  pp. 89-94, Oct. 1979. A .  Stolmeyer, "A twin-well CMOS process using high energy ion implantation", IEEE Trans. Electron Devices, vol ED-33, pp 450-457, April 1988. 

A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements

NARCIS 

1 um MOSFET VLSI Technology: part I -An overview&quot;,

A twin-well CMOS process using high energy ion implantation&quot;,

Comprehensive Test Pattern and Approach .~ for characterizing SOS Technology&quot;,

Comprehensive testpatterns with modular teststructures: The 2 by N probe pad array approach.&quot;,

Higher harmonic generation in CMOS/SOS ring oscillators&quot;,

The Application pf Microelectronic Test Structures For Propagation Delay Measurements&quot;,

http://purl.utwente.nl/publications/56088

A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements

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