PLC Implementation of Supervisory Control for a Dynamic Power Flow Controller using a Modular Approach

Dynamic Power Flow Controller (DPFC) provides steady-state and dynamic power flow control for power lines and is considered as a Flexible AC Transmission System (FACTS) controller. This paper deals with control of a standard DPFC using a Discrete Event System model. The Supervisory Control of DES has been used to implement Modular supervisors for the DPFC. Despite the fact that the SCT is well consolidated, with a large number of publications focusing on the theoretical aspects, the industrial application is unknown. It is mainly due to the complexity of the theory. The numbers of states and events to be controlled are very large even for the seemingly simple systems. In recent years, a model for modular approach to the Supervisory Control for performing the formal synthesis of Supervisors has been proposed. Programmable Logic Controllers are used for the physical implementation of the controllers. Some problems in physical realization of Supervisors in PLCs are dealt with

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS'89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches

Reliability considerations in the design, assembly, and testing of the mariner iv power system

Reliability considerations in design, assembly, and testing of Mariner IV power syste

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

Requirements Study for System Implementation of an Atmospheric Laser Propagation Experiment Program, Volume II

Program planning, ground support and airborne equipment for laser space communication syste

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US