520 research outputs found
Constraint solving over multi-valued logics - application to digital circuits
Due to usage conditions, hazardous environments or intentional causes, physical and virtual systems are subject to faults in their components, which may affect their overall behaviour. In a ‘black-box’ agent modelled by a set of propositional logic rules, in which just a subset of components is externally visible, such faults may only be recognised by examining some output function of the agent. A (fault-free) model of the agent’s system provides the expected output given some input. If the real output differs from that predicted output, then the system is faulty. However, some faults may only become apparent in the system output when appropriate inputs are given. A number of problems regarding both testing and diagnosis thus arise, such as testing a fault, testing the whole system, finding possible faults and differentiating them to locate the correct one. The corresponding optimisation problems of finding solutions that require minimum resources are also very relevant in industry, as is minimal diagnosis. In this dissertation we use a well established set of benchmark circuits to address such diagnostic related problems and propose and develop models with different logics that we formalise and generalise as much as possible. We also prove that all techniques generalise to agents and to multiple faults. The developed multi-valued logics extend the usual Boolean logic (suitable for faultfree models) by encoding values with some dependency (usually on faults). Such logics thus allow modelling an arbitrary number of diagnostic theories. Each problem is subsequently solved with CLP solvers that we implement and discuss, together with a new efficient search technique that we present. We compare our results with other approaches such as SAT (that require substantial duplication of circuits), showing the effectiveness of constraints over multi-valued logics, and also the adequacy of a general set constraint solver (with special inferences over set functions such as cardinality) on other problems. In addition, for an optimisation problem, we integrate local search with a constructive approach (branch-and-bound) using a variety of logics to improve an existing efficient tool based on SAT and ILP
RON-BEAM DEBUG AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS
A current research project at IMAG/TIM3 Laboratory aims at an integrated test system
combining the use of the Scanning Electron Microscope (SEM), used in voltage contrast
mode, with a new high-level approach of fault location in complex VLSI circuits, in order
to reach a complete automated diagnosis process.
Two research themes are induced by this project, which are: prototype validation of
known circuits, on which CAD information is available, and failure analysis of unknown
circuits, which are compared to reference circuits.
For prototype validation, a knowledge-based approach to fault location is used.
Concerning failure analysis, automatic image comparison based on pattern recog-
nition techniques is performed.
The purpose of the paper is to present these two methodologies, focusing on the
SEM-based data acquisition process
Fast algorithms for retiming large digital circuits
The increasing complexity of VLSI systems and shrinking time to market requirements demand good optimization tools capable of handling large circuits. Retiming is a powerful transformation that preserves functionality, and can be used to optimize sequential circuits for a wide range of objective functions by judiciously relocating the memory elements. Leiserson and Saxe, who introduced the concept, presented algorithms for period optimization (minperiod retiming) and area optimization (minarea retiming). The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization;The first part of this thesis defines the relationship between the Leiserson-Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same linear program formulation as the Leiserson-Saxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints in this linear program. This allows minarea retiming of circuits with over 56,000 gates in under fifteen minutes;The movement of flip-flops in control logic changes the state encoding of finite state machines, requiring the preservation of initial (reset) states. In the next part of this work the problem of minimizing the number of flip-flops in control logic subject to a specified clock period and with the guarantee of an equivalent initial state, is formulated as a mixed integer linear program. Bounds on the retiming variables are used to guarantee an equivalent initial state in the retimed circuit. These bounds lead to a simple method for calculating an equivalent initial state for the retimed circuit;The transparent nature of level sensitive latches enables level-clocked circuits to operate faster and require less area. However, this transparency makes the operation of level-clocked circuits very complex, and optimization of level-clocked circuits is a difficult task. This thesis also presents efficient algorithms for retiming large level-clocked circuits. The relationship between retiming and clock skew optimization for level-clocked circuits is defined and utilized to develop efficient retiming algorithms for period and area optimization. Using these algorithms a circuit with 56,000 gates could be retimed for minimum period in under twenty seconds and for minimum area in under 1.5 hours
Identification of Soft-Error at Gate Level
Due to shrinking feature size and significant reduction in noise margins, as we are moving into very deep sub-micron technology, circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, due to technology scaling, logic circuits have become equally susceptible to soft errors. Moreover, enhanced usage of commercial off the shelf (COTS) electronic components for avionics has also increased the importance of analyzing soft errors in hardware circuits. Conventionally, understanding soft error glitches requires circuit level modeling, which requires information available only at late stages in the design flow. Instead of this approach some researchers have produced modeling techniques using Reduced Order Binary Decision Diagrams (ROBDD) and Algebraic Decision Diagrams (ADD), which does allow analyzing soft error at an earlier stage in design flow. In this thesis, a new methodology for modeling soft errors glitch propagation path using Multiway Decision Graphs is introduced. This modeling technique is applicable on both combinational
and asynchronous circuits. The proposed glitch propagation path modeling technique jointly takes care of logical and electrical masking. Our methodology involves new ways of injecting glitches including glitch injection in feedback paths of asynchronous circuits. This work presents a complete framework to exhaustively provide all the possible sequences of signals that lead to the possibility of glitch propagation to the primary output in combinational and asynchronous circuits. In addition, a new tool is developed based on the proposed methodology called Soft Error Glitch-Propagating Path Finder (SEGP-Finder) to automate the identification of these sequences of signals. This work helps designers identify the vulnerable circuit
paths at the logic abstraction level. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of possibilities. By applying our methodology on different combinational and asynchronous circuits an improvement in terms of possible-fault injection vectors is observed. As an example, approximately 8% of all the possible input vectors and sequences is required for obtaining exhaustive glitch propagation path identification in a representative implementation of a bundled data asynchronous circuit. To the best of our knowledge, this is the first time MDG based decision diagram based soft error identification approach is proposed for combinational and asynchronous circuits
論理シミュレーションとハードウェア記述言語に関する研究
京都大学0048新制・論文博士工学博士乙第7496号論工博第2471号新制||工||842(附属図書館)UT51-91-E273(主査)教授 矢島 脩三, 教授 津田 孝夫, 教授 田丸 啓吉学位規則第5条第2項該当Kyoto UniversityDFA
Proof Planning for Automating Hardware Verification
Centre for Intelligent Systems and their ApplicationsIn this thesis we investigate the applicability of proof planning to automate the verification of hardware systems. Proof planning is a meta-level reasoning technique which captures patterns of proof common to a family of theorems. It contributes to the automation of proof by incorporating and extending heuristics found in the Nqthm theorem prover and using them to guide a tactic-based theorem prover in the search for a proof. We have addressed the automation of proof for hardware verification from a proof planning perspective, and have applied the strategies and search control mechanisms of proof planning to generate automatically customised tactics which prove conjectures about the correctness of many types of circuits. The contributions of this research can be summarised as follows:
(1) we show by experimentation the applicability of the proof planning ideas to verify automatically hardware designs;(2)we develop and use a methodology based on the concept of proof engineering using proof planning to verify various combinational and sequential circuits which include: arithmetic circuits (adders, subtracters, multipliers, dividers, factorials), data-path components arithmetic logic units shifters, processing units) and a simple microprocessor system; and (3) we contribute to the profiling of the Clam proof planning system by improving its robustness and efficiency in handling large terms and proofs. In verifying hardware, the user formalises a problem by writing the specification, the implementation and the conjecture, using a logic language, and asks Clam to compose a tactic to prove the conjecture. This tactic is then executed by the Oyster prover. To compose a tactic, Clam uses a set of methods which implement the heuristics that specify general-purpose tactics, and AI planning mechanisms. Search is controlled by a type of annotated rewriting called rippling, which controls the selective application of rewrite scaled wave rules. We have extended some of the Clam's methods to verify circuits.The size of the proofs were orders of magnitude larger than the proofs that had been attempted before with proof planning, and are comparable with similar verification proofs obtained by other systems but using fewer lemmas and less interaction. Proof engineering refers to the application of formal proof for system design and verification. We propose a proof engineering methodology which consists of partitioning the automation of formal proof into three different kind of tasks: user, proof and systems tasks.User tasks have to do with formalising a particular verification problem and using a formal tool to obtain a proof. Proof tasks refer to the tuning of proof techniques (e.g. methods and tactics)to help obtain a proof. Systems tasks have to do with the modification of a formal tool system. By making this distinction explicit, proof development is more manageable. We conjecture that our approach is widely applicable and can be integrated into formal verification environments to improve automation facilities, and be utilised to verify commercial and safety-critical hardware systems in industrial settings
Algorithm to layout (ATL) systems for VLSI design
PhD ThesisThe complexities involved in custom VLSI design together with the
failure of CAD techniques to keep pace with advances in the fabrication
technology have resulted in a design bottleneck. Powerful tools are
required to exploit the processing potential offered by the densities now
available. Describing a system in a high level algorithmic notation
makes writing, understanding, modification, and verification of a design
description easier. It also removes some of the emphasis on the physical
issues of VLSI design, and focus attention on formulating a correct and
well structured design. This thesis examines how current trends in CAD
techniques might influence the evolution of advanced Algorithm To Layout
(ATL) systems. The envisaged features of an example system are
specified. Particular attention is given to the implementation of one
its features COPTS (Compilation Of Occam Programs To Schematics).
COPTS is capable of generating schematic diagrams from which an
actual layout can be derived. It takes a description written in a subset
of Occam and generates a high level schematic diagram depicting its
realisation as a VLSI system. This diagram provides the designer with
feedback on the relative placement and interconnection of the operators
used in the source code. It also gives a visual representation of the
parallelism defined in the Occam description. Such diagrams are a
valuable aid in documenting the implementation of a design.
Occam has also been selected as the input to the design system that
COPTS is a feature of. The choice of Occam was made on the assumption
that the most appropriate algorithmic notation for such a design system
will be a suitable high level programming language. This is in contrast
to current automated VLSI design systems, which typically use a hardware
des~ription language for input. These special purpose languages
currently concentrate on handling structural/behavioural information and
have limited ability to express algorithms. Using a language such as
Occam allows a designer to write a behavioural description which can be
compiled and executed as a simulator, or prototype, of the system. The
programmability introduced into the design process enables designers to
concentrate on a design's underlying algorithm. The choice of this
algorithm is the most crucial decision since it determines the
performance and area of the silicon implementation.
The thesis is divided into four sections, each of several chapters.
The first section considers VLSI design complexity, compares the expert
systems and silicon compilation approaches to tackling it, and examines
its parallels with software complexity. The second section reviews the
advantages of using a conventional programming language for VLSI system
descriptions. A number of alternative high level programming languages
are considered for application in VLSI design. The third section defines
the overall ATL system COPTS is envisaged to be part of, and considers
the schematic representation of Occam programs. The final section
presents a summary of the overall project and suggestions for future work
on realising the full ATL system
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
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