Test Generation Algorithm Based on SVM with compressing Sample Space Methods

Test generation algorithm based on the SVM (support vector machine) generates test signals derived from the sample space of the output responses of the analog DUT. When the responses of the normal circuits are similar to those of the faulty circuits (i.e., the latter have only small parametric faults), the sample space is mixed and traditional algorithms have difficulty distinguishing the two groups. However, the SVM provides an effective result. The sample space contains redundant data, because successive impulse-response samples may get quite close. The redundancy will waste the needless computational load. So we propose three difference methods to compress the sample space. The compressing sample space methods are Equidistant compressional method, k-nearest neighbors method and maximal difference method. Numerical experiments prove that maximal difference method can ensure the precision of the test generation

Dynamic Test Scheduling for Analog Circuits for Improved Test Quality

Abstract-In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method

Built-In Self-Test Solution for CMOS MEMS Sensors

This thesis presents a new readout circuit with integrated Built-in Self-Test (BIST) structure for capacitive Micro-Electro-Mechanical Systems (MEMS). In the proposed solution instead of commonly used voltage control signals to test the device, charge control stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of MEMS structural collapse in the test phase. Measurement results using a prototype fabricated in TSMC 65nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance