Automated synthesis and optimization of multilevel logic circuits.

With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synthesis plays an even more important role due to its flexibility and compactness.The history of symbolic logic and some typical techniques for multilevel logic synthesisare reviewed. These methods include algorithmic approach; Rule-Based approach; BinaryDecision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approachand several perturbation applications.One new kind of don't cares (DCs), called functional DCs has been proposed for multilevellogic synthesis. The conventional two-level cubes are generalized to multilevel cubes.Then functional DCs are generated based on the properties of containment. The conceptof containment is more general than unateness which leads to the generation of newDCs. A separate C program has been developed to utilize the functional DCs generatedas a Boolean function is decomposed for both single output and multiple output functions.The program can produce better results than script.rugged of SIS, developed by UC Berkeley,both in area and speed in less CPU time for a number of testcases from MCNC andIWLS'93 benchmarks.In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantagesover the standard Boolean logic based on AND JOR operations. A bidirectionalconversion algorithm between these two paradigms is presented based on the concept of polarityfor sum-of-products (SOP) Boolean functions, multiple segment and multiple pointerfacilities. Experimental results show that the algorithm is much faster than the previouslypublished programs for any fixed polarity. Based on this algorithm, a new technique calledredundancy-removal is applied to generalize the idea to very large multiple output Booleanfunctions. Results for benchmarks with up to 199 inputs and 99 outputs are presented.Applying the preceding conversion program, any Boolean functions can be expressedby fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function andthe number of product terms depends on these polarities. The problem of exact polarityminimization is computationally extensive and current programs are only suitable whenn :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logicand Reed-Muller logic, a fast algorithm is developed and implemented in C language whichcan find the best polarity for multiple output functions. Benchmark examples of up to 25inputs and 29 outputs run on a personal computer are given.After the best polarity for a Boolean function is calculated, this function can be furthersimplified using mixed polarity methods by combining the adjacent product terms. Hence,an efficient program is developed based on decomposition strategy to implement mixedpolarity minimization for both single output and very large multiple output Boolean functions.Experimental results show that the numbers of product terms are much less thanthe results produced by ESPRESSO for some categories of functions

Algorithms in computer-aided design of VLSI circuits.

With the increased complexity of Very Large Scale Integrated (VLSI) circuits,Computer Aided Design (CAD) plays an even more important role. Top-downdesign methodology and layout of VLSI are reviewed. Moreover, previouslypublished algorithms in CAD of VLSI design are outlined.In certain applications, Reed-Muller (RM) forms when implemented withAND/XOR or OR/XNOR logic have shown some attractive advantages overthe standard Boolean logic based on AND/OR logic. The RM forms implementedwith OR/XNOR logic, known as Dual Forms of Reed-Muller (DFRM),is the Dual form of traditional RM implemented with AND /XOR.Map folding and transformation techniques are presented for the conversionbetween standard Boolean and DFRM expansions of any polarity. Bidirectionalmulti-segment computer based conversion algorithms are also proposedfor large functions based on the concept of Boolean polarity for canonicalproduct-of-sums Boolean functions. Furthermore, another two tabular basedconversion algorithms, serial and parallel tabular techniques, are presented forthe conversion of large functions between standard Boolean and DFRM expansionsof any polarity. The algorithms were tested for examples of up to 25variables using the MCNC and IWLS'93 benchmarks.Any n-variable Boolean function can be expressed by a Fixed PolarityReed-Muller (FPRM) form. In order to have a compact Multi-level MPRM(MMPRM) expansion, a method called on-set table method is developed.The method derives MMPRM expansions directly from FPRM expansions.If searching all polarities of FPRM expansions, the MMPRM expansions withthe least number of literals can be obtained. As a result, it is possible to findthe best polarity expansion among 2n FPRM expansions instead of searching2n2n-1 MPRM expansions within reasonable time for large functions. Furthermore,it uses on-set coefficients only and hence reduces the usage of memorydramatically.Currently, XOR and XNOR gates can be implemented into Look-Up Tables(LUT) of Field Programmable Gate Arrays (FPGAs). However, FPGAplacement is categorised to be NP-complete. Efficient placement algorithmsare very important to CAD design tools. Two algorithms based on GeneticAlgorithm (GA) and GA with Simulated Annealing (SA) are presented for theplacement of symmetrical FPGA. Both of algorithms could achieve comparableresults to those obtained by Versatile Placement and Routing (VPR) toolsin terms of the number of routing channel tracks

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Fundamental Approaches to Software Engineering

This open access book constitutes the proceedings of the 23rd International Conference on Fundamental Approaches to Software Engineering, FASE 2020, which took place in Dublin, Ireland, in April 2020, and was held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020. The 23 full papers, 1 tool paper and 6 testing competition papers presented in this volume were carefully reviewed and selected from 81 submissions. The papers cover topics such as requirements engineering, software architectures, specification, software quality, validation, verification of functional and non-functional properties, model-driven development and model transformation, software processes, security and software evolution

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing