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Testability considerations for implementing an embedded memory subsystem
textThere are a number of testability considerations for VLSI design,
but test coverage, test time, accuracy of test patterns and
correctness of design information for DFD (Design for debug) are
the most important ones in design with embedded memories. The goal
of DFT (Design-for-Test) is to achieve zero defects. When it comes
to the memory subsystem in SOCs (system on chips), many flavors of
memory BIST (built-in self test) are able to get high test
coverage in a memory, but often, no proper attention is given to
the memory interface logic (shadow logic). Functional testing and
BIST are the most prevalent tests for this logic, but functional
testing is impractical for complicated SOC designs. As a result,
industry has widely used at-speed scan testing to detect delay
induced defects. Compared with functional testing, scan-based
testing for delay faults reduces overall pattern generation
complexity and cost by enhancing both controllability and
observability of flip-flops. However, without proper modeling of
memory, Xs are generated from memories. Also, when the design has
chip compression logic, the number of ATPG patterns is increased
significantly due to Xs from memories. In this dissertation, a
register based testing method and X prevention logic are presented
to tackle these problems.
An important design stage for scan based testing with memory
subsystems is the step to create a gate level model and verify
with this model. The flow needs to provide a robust ATPG netlist
model. Most industry standard CAD tools used to analyze fault
coverage and generate test vectors require gate level models.
However, custom embedded memories are typically designed using a
transistor-level flow, there is a need for an abstraction step to
generate the gate models, which must be equivalent to the actual
design (transistor level). The contribution of the research is a
framework to verify that the gate level representation of custom
designs is equivalent to the transistor-level design.
Compared to basic stuck-at fault testing, the number of patterns
for at-speed testing is much larger than for basic stuck-at fault
testing. So reducing test and data volume are important. In this
desertion, a new scan reordering method is introduced to reduce
test data with an optimal routing solution. With in depth
understanding of embedded memories and flows developed during the
study of custom memory DFT, a custom embedded memory Bit Mapping
method using a symbolic simulator is presented in the last chapter
to achieve high yield for memories.Electrical and Computer Engineerin
Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits.
This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL)
Efficient alternative wiring techniques and applications.
Sze, Chin Ngai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 80-84) and index.Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiCurriculum Vitae --- p.ivList of Figures --- p.ixList of Tables --- p.xiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation and Aims --- p.1Chapter 1.2 --- Contribution --- p.8Chapter 1.3 --- Organization of Dissertation --- p.10Chapter 2 --- Definitions and Notations --- p.11Chapter 3 --- Literature Review --- p.15Chapter 3.1 --- Logic Reconstruction --- p.15Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18Chapter 3.2.3 --- REWIRE --- p.21Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22Chapter 3.3 --- Graph-based Alternative Wiring --- p.24Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25Chapter 4.1 --- Source Node Implication --- p.25Chapter 4.1.1 --- Introduction --- p.25Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32Chapter 4.2 --- Destination Node Implication --- p.35Chapter 4.2.1 --- Introduction --- p.35Chapter 4.2.2 --- Destination Node Relationship --- p.35Chapter 4.2.3 --- Destination Node Implication-tree --- p.39Chapter 4.2.4 --- Selection of Alternative Wire --- p.41Chapter 4.3 --- The Algorithm --- p.43Chapter 4.3.1 --- IB AW Implementation --- p.43Chapter 4.3.2 --- Experimental Results --- p.43Chapter 4.4 --- Conclusion --- p.45Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47Chapter 5.1 --- Introduction --- p.47Chapter 5.2 --- Notations and Definitions --- p.48Chapter 5.3 --- Alternative Wire Patterns --- p.50Chapter 5.4 --- Construction of Minimal Patterns --- p.54Chapter 5.4.1 --- Minimality of Patterns --- p.54Chapter 5.4.2 --- Minimal Pattern Formation --- p.56Chapter 5.4.3 --- Pattern Extraction --- p.61Chapter 5.5 --- Experimental Results --- p.63Chapter 5.6 --- Conclusion --- p.63Chapter 6 --- Logic Optimization by GBAW --- p.66Chapter 6.1 --- Introduction --- p.66Chapter 6.2 --- Logic Simplification --- p.67Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71Chapter 6.4 --- GBAW Optimization Algorithm --- p.73Chapter 6.5 --- Experimental Results --- p.73Chapter 6.6 --- Conclusion --- p.76Chapter 7 --- Conclusion --- p.78Bibliography --- p.80Chapter A --- VLSI Design Cycle --- p.85Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87Chapter B.1 --- 0-local Pattern --- p.87Chapter B.2 --- 1-local Pattern --- p.88Chapter B.3 --- 2-local Pattern --- p.89Chapter B.4 --- Fanout-reconvergent Pattern --- p.90Chapter C --- New Alternative Wire Patterns --- p.91Chapter C.1 --- Pattern Cluster C1 --- p.91Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95Chapter C.2 --- Pattern Cluster C2 --- p.98Chapter C.3 --- Pattern Cluster C3 --- p.99Chapter C.4 --- Pattern Cluster C4 --- p.104Chapter C.5 --- Pattern Cluster C5 --- p.105Glossary --- p.106Index --- p.10
A Sixteen-Valued Algorithm for Test Generation in Combinational Circuits
A 16-valued logic system for testing combinational circuits is presented. This logic system has been used to develop SIMPLE, an efficient test generation algorithm for single stuck-at faults. The proposed scheme for testing stuck-at faults is based on imposing all the constraints that must be satisfied in order to sensitize a path from a fault site to a primary output. Consequently all deterministic implications are fully considered prior to the enumeration process. The resulting ability to identify inconsistencies prior to enumeration improves the possibility of quicker identification of redundant faults. In order to prune the search space we have introduced several speed-up techniques that effectively combine the information provided by the deterministic path sensitization and that obtained from the circuit topology. Some properties of undetectable faults are presented and methods to identify them without actual test generation are proposed
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
SRAM-based FPGAs are increasingly relevant in a growing number of safety-critical application fields, ranging from automotive to aerospace. These application fields are characterized by a harsh radiation environment that can cause the occurrence of Single Event Upsets (SEUs) in digital devices. These faults have particularly adverse effects on SRAM-based FPGA systems because not only can they temporarily affect
the behaviour of the system by changing the contents of flip-flops or memories, but they can also permanently change the functionality implemented by the system itself, by changing the content of the configuration memory. Designing safety-critical applications requires accurate methodologies to evaluate the system’s sensitivity to SEUs as early as possible during the design process. Moreover it is necessary to detect the occurrence of SEUs during the system life-time. To this purpose test patterns should be generated during the design process, and then applied to the inputs of the system during its operation. In this thesis we propose a set of software tools that could be used by designers of SRAM-based FPGA safety-critical applications to assess the sensitivity to SEUs of the system and to generate test patterns for in-service testing. The main feature of these tools is that they implement a model of SEUs affecting the configuration bits controlling the logic and routing resources of an FPGA device that has been demonstrated to be much more accurate than the classical stuck-at and open/short models, that are
commonly used in the analysis of faults in digital devices. By keeping this accurate
fault model into account, the proposed tools are more accurate than similar academic and commercial tools today available for the analysis of faults in digital circuits, that do not take into account the features of the FPGA technology..
In particular three tools have been designed and developed: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, a simulator of SEUs affecting the configuration memory of an SRAM-based FPGA system
for the early assessment of the sensitivity to SEUs; (ii) UA2TPG: Untestability Analyzer
and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, a static analysis tool for the identification of the untestable SEUs and for the automatic generation of test patterns for in-service testing of the 100% of the testable SEUs; and (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, a Genetic Algorithm-based Environment for the generation of an optimized set of test patterns for in-service testing of SEUs. The proposed tools have been applied to some circuits from the ITC’99 benchmark. The results obtained from these experiments have been compared with results
obtained by similar experiments in which we considered the stuck-at fault model, instead
of the more accurate model for SEUs. From the comparison of these experiments we have been able to verify that the proposed software tools are actually more accurate than similar tools today available. In particular the comparison between results obtained using ASSESS with those obtained by fault injection has shown that the proposed fault simulator has an average error of 0:1% and a maximum error of 0:5%, while using a stuck-at fault simulator the average error with respect of the fault injection experiment has been 15:1% with a maximum error of 56:2%. Similarly the comparison between the results obtained using UA2TPG for the accurate SEU model, with the results obtained for stuck-at faults has shown an average difference of untestability of 7:9% with a maximum of 37:4%. Finally the comparison between
fault coverages obtained by test patterns generated for the accurate model of SEUs and the fault coverages obtained by test pattern designed for stuck-at faults, shows that the former detect the 100% of the testable faults, while the latter reach an average fault coverage of 78:9%, with a minimum of 54% and a maximum of 93:16%
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
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