Penelope: The NBTI-aware processor

Transistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias temperature instability) is one of the most important sources of failure affecting transistors. NBTI degrades PMOS transistors whenever the voltage at the gate is negative (logic inputPeer ReviewedPostprint (published version

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis

A depletable pool of adenosine in area CA1 of the rat hippocampus

Adenosine plays a major modulatory and neuroprotective role in the mammalian CNS. During cerebral metabolic stress, such as hypoxia or ischemia, the increase in extracellular adenosine inhibits excitatory synaptic transmission onto vulnerable neurons via presynaptic adenosine A1 receptors, thereby reducing the activation of postsynaptic glutamate receptors. Using a combination of extracellular and whole-cell recordings in the CA1 region of hippocampal slices from 12- to 24-d-old rats, we have found that this protective depression of synaptic transmission weakens with repeated exposure to hypoxia, thereby allowing potentially damaging excitation to both persist for longer during oxygen deprivation and recover more rapidly on reoxygenation. This phenomenon is unlikely to involve A1 receptor desensitization or impaired nucleoside transport. Instead, by using the selective A1 antagonist 8-cyclopentyl-1,3-dipropylxanthine and a novel adenosine sensor, we demonstrate that adenosine production is reduced with repeated episodes of hypoxia. Furthermore, this adenosine depletion can be reversed at least partially either by the application of exogenous adenosine, but not by a stable A1 agonist, N6-cyclopentyladenosine, or by endogenous means by prolonged (2 hr) recovery between hypoxic episodes. Given the vital neuroprotective role of adenosine, these findings suggest that depletion of adenosine may underlie the increased neuronal vulnerability to repetitive or secondary hypoxia/ischemia in cerebrovascular disease and head injury

Superradiant Undulator Radiation for Selective THz Control Experiments at XFELs

The generation of frequency-tunable, narrow-bandwidth and carrier-envelope-phase stable THz pulses with fields in the MV/cm regime that can be appropriately timed to the femtosecond X-ray pulses from free-electron-lasers is of highest scientific interest. It will enable to follow the electronic and structural dynamics stimulated by (non)linear selective excitations of matter on few femtosecond time and {\AA}ngstrom length scales. In this article, a scheme based on superradiant undulator radiation generated just after the XFEL is proposed. The concept utilizes cutting edge superconducting undulator technology and provides THz pulses in a frequency range between 3 and 30 THz with exceptional THz pulse energies. Relevant aspects for realization and operation are discussed point by point on the example of the European XFEL

Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses