Representação de aplicações C/C++ segundo um grafo para execução em sistemas heterogéneos

São cada vez mais as areas de investigação que recorrem a sistemas computacionais de elevada performance para resolver complexos modelos matemáticos. Para dar resposta a problemas cada vez mais complicados, tem havido um grande desenvolvimento no hardware para os sistemas computacionais de elevado desempenho, tecnologias como CUDA - Compute Unified Device Architecture - ou FPGA - Field-programmable gate array - têm-se tornado parte integrante dos tradicionais clusters informáticos. Dando assim origem a sistemas denominados heterogéneos. Dadas as especificidades deste tipo de infraestruturas, é necessário repensar a forma de execução de tarefas, de forma a garantir um proveito significativo das novas soluções: conseguir mapear inteligentemente tarefas com os recursos que melhor as consigam resolver permite obter, não só um melhor desempenho computacional, mas também reduzir custos energéticos do sistema. Esta dissertação pretende explorar uma forma de representação de código C/C++ através de grafos dirigidos que permitam posteriormente a utilização de algoritmos de escalonamento para sistemas heterogéneos (PEFT, HEFT, etc.). Para isso, propõe-se uma analise e identificação de regiões criticas através da árvore sintática abstrata (AST) obtida da compilação do código com o compilador Clang. Esta analise, juntamente com informação obtida de modelos computacionais, permitem então gerar perfis otimizados para a execução do código. Pretende-se assim, obter uma ferramenta que tendo em conta a especificidade do código a executar, e a arquitetura do ambiente de execução produza um grafo que represente as várias tarefas de um programa, as suas dependências e as comunicações de dados necessários entre as várias tarefas. Este grafo possibilita posteriormente a utilização de algoritmos de escalonamento que otimizam a sua execução numa arquitetura heterogénea

Верификация проектов и построение тестов контроля СБИС на уровне RTL

Предлагается метод верификации проектов и направленного построения тестов контроля СБИС, представленных на уровне RTL на языке VHDL. Задача построения тестов и верификации проектов решается на основе КНФ – выполнимости некоторой системы булевых функций

Построение тестов и верификация потоковых моделей цифровых устройств на языке VHDL

Предлагается единый подход к верификации проектов и направленному построению тестов контроля СБИС, представленных в потоковом виде на уровне RTL на языке VHDL с использованием арифметических, логических операторов и оператора If. Задача построения тестов и верификации проектов решается на основе КНФ-выполнимости некоторой системы булевых функций

ПОСТРОЕНИЕ ТЕСТОВ И ВЕРИФИКАЦИЯ ПОТОКОВЫХ МОДЕЛЕЙ ЦИФРОВЫХ УСТРОЙСТВ НА ЯЗЫКЕ VHDL

Предлагается единый подход к верификации проектов и направленному построению тестовконтроля СБИС, представленных в потоковом виде на уровне RTL на языке VHDL с использованием арифметических, логических операторов и оператора If. Задача построения тестов и верификации проектов решается на основе КНФ-выполнимости некоторой системы булевых функций

Design for Implementation of Image Processing Algorithms

Color image processing algorithms are first developed using a high-level mathematical modeling language. Current integrated development environments offer libraries of intrinsic functions, which on one hand enable faster development, but on the other hand hide the use of fundamental operations. The latter have to be detailed for an efficient hardware and/or software physical implementation. Based on the experience accumulated in the process of implementing a segmentation algorithm, this thesis outlines a design for implementation methodology comprised of a development flow and associated guidelines. The methodology enables algorithm developers to iteratively optimize their algorithms while maintaining the level of image integrity required by their application. Furthermore, it does not require algorithm developers to change their current development process. Rather, the design for implementation methodology is best suited for optimizing a functionally correct algorithm, thus appending to an algorithm developer\u27s design process of choice. The application of this methodology to four segmentation algorithm steps produced measured results with 2-D correlation coefficients (CORR2) better than 0.99, peak-signal-to-noise-ratio (PSNR) better than 70 dB, and structural-similarity-index (SSIM) better than 0.98, for a majority of test cases

The hArtes Tool Chain

This chapter describes the different design steps needed to go from legacy code to a transformed application that can be efficiently mapped on the hArtes platform

An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that functional languages are especially suitable for implementation of domain-specific languages, including HDLs. Casestudies examining the implementation complexity of HEP-specific language extensions to the functional HDCaml HDL will prove the viability of the suggested approach