Innovative Strategies in Technical and Vocational Education and Training for Accelerated Human Resource Development in South Asia: Bangladesh

The reports herein provide in-depth analyses of the state of technical and vocational education and training (TVET) and higher education in Bangladesh, Nepal, and Sri Lanka. Each country has two reports covering TVET and higher education which were presented in the three country-level workshops during the first week of December 2012: Sri Lanka (1 December), Nepal (3 December), and Bangladesh (5 December). Participants from government, the private sector, academe, and development partners discussed and validated the findings and supported the recommendations as well as identified additional next steps. In TVET, issues range from insufficient teachers and trainers in Bangladesh to lack of quality monitoring system in Nepal, and to inadequate industry participation in Sri Lanka. Among the common issues identified are weak quality assurance mechanisms, low employment rate of graduates, lack of information about demand (leading to a mismatch between training and available jobs), expensive and long-term training that excludes the poor and marginalized, weak institutional arrangements, and inadequate provision of high-quality TVET to manage and scale up training programs. Higher education is equally affected by various constraints ranging from lack of accountability for performance among institutions in Bangladesh to high politicization in Nepal, and to weak quality assurance mechanisms in Sri Lanka. Common issues identified are regional disparities in access, high cost in private higher education institutions, and poor quality and relevance as well as lack of emphasis on courses that promote entrepreneurship. Key recommendations of the reports include implementation of a national quality assurance system, establishing a reliable skills data and labor market information system, effective financing schemes, encouraging public–private partnerships, and international benchmarking and mutual recognition for global competitiveness. In TVET, the key priorities are strengthening private training provision with clearly identified and mandated apex agency to effectively coordinate and scale up training programs, development of national competency standards, and building the capacity of TVET institutions. In higher education, the key priorities are developing research capacity, improved targeting of financial assistance to students, adopting formula funding in allocating public funding to universities, promoting accountability and autonomy among higher education institutions, and depoliticization of the higher education system

Hydrographic Requirements for Planning and Development in African Coastal and Inland Waters

Hydrography involves collecting data about the depth of water, the position of submerged dangers to navigation and the movement of water in the world’s continental shelves and oceans, and publishing such data in the form of nautical charts. Such charts are essential for the safety of passengers and cargoes, for the exploration and exploitation of marine resources and the protection of marine environment. The latest charts available off the coasts and in the inland navigable waters of Africa are very often based on data collected up to 150 years ago. There are only five hydrographic ships and 13 hydrographic launches to survey 10,250,000 km2 of African countries’ Exclusive Economic Zones; only seven African maritime countries have any capability to produce their own nautical charts. In order to start to improve this highly undesirable restraint on the African economy, it is suggested that each African maritime country should form a national Hydrographic Committee and seek expert advice on creating a national hydrographic capability. It is also suggested that three Regional Hydrographic Centres should be established, attached to existing Regional Centres in East, West and North Africa, to provide on-going advice within the Region and to undertake the maintenance of the highly specialized hydrographic surveying equipment needed and the training of nautical cartography. The International Hydrographic Organization is willing to provide advice on the development of these facilities

Zuverlässigkeitsbewertung von Fahrzeug-zu-Fahrzeug Kommunikation

V2V communication enables a plethora of cooperative applications aimed at reducing road hazard situations as well as enhancing traffic efficiency and individual driving comfort, expanding therewith the boundaries of Advanced Driver Assistance Systems (ADAS). These applications will be supported by IEEE 802.11p, a standard operating in the 5.9GHz frequency band and adapted for the highly dynamic vehicular environment. The focus of this work is V2V safety applications, which have already gained a major attention from the industry, academia, as well as standardization bodies. Being a subject of wireless communication the performance of V2V applications directly depends on the communication link quality and the packet distribution pattern. Therefore, the main purpose of this thesis is to develop an effective communication link reliability assessment method and analyze to what extent V2V communication is feasible to satisfy the reliability requirements of safety applications. Furthermore, we investigate the effectiveness of the proposed assessment method when applied for real-time communication link reliability prediction. In particular, in this work we establish the link between classical network performance metrics and specific application reliability requirements and derive a set of advanced assessment metrics. Afterwards, we investigate through these metrics how different environmental factors affect application reliability based on the measurement data, which was obtained in elaborated real-world measurement campaigns and in different non-line-of-sight scenarios. Using the suggested metrics further in this work we additionally analyze the achievable application reliability of the V2V safety applications in congested network scenarios through the simulation study. Based on these results we also define the most favorable combinations of the network parameters to support reliable operation of these applications. Finally, in this thesis we examine to what extent the suggested metrics are suitable for applications while operating in real time. We develop and implement two frameworks for prediction of the communication link reliability, based on the data that was obtained over the 4.5 months of the simTD project field trials. Furthermore, we apply both frameworks to other measurement data, which was obtained outside the simTD project and assess the effectiveness of both frameworks under independent realistic conditions.Car2Car-Kommunikation ermöglicht eine Vielzahl von kooperativen Anwendungen, welche auf die Unfallverminderung, Verbesserung der Verkehrseffizienz sowie den individuellen Fahrkomfort abzielen und damit die Grenzen von aktiven Fahrerassistenzsystemen erweitern. Im Fokus dieser Dissertation stehen Car2Car-Sicherheitsanwendungen, denen heutzutage bereits große Aufmerksamkeit von Seiten der Industrie, Forschung und diversen Normierungsgremien geschenkt wird. Da alle diese Anwendungen auf drahtloser Kommunikation basieren, ist ihre Leistungsfähigkeit direkt von der Qualität der Kommunikationsverbindung sowie dem Paketverteilungsmuster abhängig. Daher liegt der Hauptfokus dieser Arbeit in der Entwicklung effektiver Methoden zur Bewertung der Kommunikationszuverlässigkeit und der Analyse, inwieweit Car2Car-Kommunikation im Allgemeinen die Anforderungen von Sicherheitsanwendungen erfüllt. Darüber hinaus untersucht diese Doktorarbeit die Effektivität der hier vorgeschlagenen Bewertungsmethoden in Bezug auf die Vorhersage der Kommunikationszuverlässigkeit in Echtzeit-Szenarien. Im Speziellen verbindet diese Arbeit die Welt der klassischen Netzwerkperformance-Metriken mit Car2Car-Anwendungsspezifischen Zuverlässigkeitsanforderungen und stellt als Ergebnis eine Reihe effektiver Bewertungskennzahlen vor. Mithilfe der vorgeschlagenen Metriken wird des Weiteren untersucht, inwieweit verschiedene Umweltfaktoren die Anwendungszuverlässigkeit beeinflussen können. Diese Untersuchung basiert auf Messdaten, die in ausführlichen Feldversuchen in verschiedenen Non-Line-of-Sight-Szenarien gewonnen wurden. Im nächsten Schritt analysiert diese Doktorarbeit die erreichbare Zuverlässigkeit der Car2Car-Sicherheitsanwendungen in Netzwerküberlastungsszenarien anhand einer Simulationsstudie. Als Ergebnis werden die spezifischen Kombinationen der verschiedenen Netzwerkparameter definiert, die einen zuverlässigen Betrieb der Car2Car-Sicherheitsanwendungen gewährleisten können. Zum Abschluss untersucht diese Dissertation, inwieweit die vorgeschlagenen Metriken für die im Echtzeit-Modus funktionierenden Anwendungen geeignet sind. Darüber hinaus werden zwei Frameworks entwickelt und implementiert, welche die Zuverlässigkeit der Kommunikationsverbindung prädizieren. Dies geschieht basierend auf Daten, die während der 4.5 Monate dauernden Feldversuche im Rahmen des simTD Projektes gewonnen wurden. Beide Frameworks werden am Ende anhand unabhängiger Messdaten auf ihre Funktionalität unter realistischen Bedingungen getestet

Investigations of Prokaryotic Defense Systems

Bacteria are constantly threatened with infection by mobile genetic elements (MGE) such as bacteriophage and plasmids. Bacteriophage and plasmids require the bacteria\u27s cellular infrastructure to replicate their genomes. Rampant replication can lead to cell death which is one reason why bacteria have developed a diverse array of immune systems to prevent or limit infection. This thesis studies three types of bacterial immune systems, type IV-A CRISPR-Cas (Clustered Regularly Interspaced Short Palindromic Repeat –CRISPR associated), type V-A2 CRISPR-Cas systems, and Wadjet systems. The type IV-A system lies adjacent to a dinG-like helicase gene. Research has shown that this system can target plasmids preventing their spread throughout a microbial population. This system is reliant upon the dinG-like gene, but how this system mechanistically prevents plasmid sharing is not understood. The type V-A2 system has been shown to be capable of editing the genome of rice by generating breaks in the DNA. How this editing takes place, and the other biochemical mechanisms of this protein are not understood either. This thesis provides the preliminary framework for studying these putative genome editing tools. Wadjet immune systems prevent the sharing of plasmids between bacteria.These systems share structural similarities with proteins responsible for separating bacterial chromosomes during cellular replication. This thesis contains the foundation for the characterization of the system by cloning genes from native host systems and then recombinantly expressing and purifying proteins

Towards Genetic Identification with Male-specific Mutations

The identification and application of new genetic variants for differentiation patrilineally related male relatives using Y chromosomal short tandem repeats (Y-STRs)

Genetically dissect disease interactions between Parastagonospora nodorum and wheat (Triticum aestivum L.)

Parastagonospora nodorum is a necrotrophic fungal pathogen of wheat (Triticum aestivum L.) and the causative agent of stagonospora nodorum blotch (SNB). P. nodorum mediates host cell death using proteinaceous effectors. Three P. nodorum effectors have been cloned: SnToxA, SnTox1 and SnTox3. SnTox3 susceptible wheat cultivars possess a dominant susceptibility allele at the Snn3-B1 locus; breeding to remove SnTox3 sensitivity could help increase P. nodorum disease resistance. The research presented here falls into three main areas: 1. Genetic mapping of SnTox3 sensitivity: the major SnTox3 sensitivity locus Snn3-B1 was fine-mapped using an association mapping panel, the Avalon x Cadenza population and a MAGIC population. These defined a 6.2 kb region on chromosome 5B explaining ≥ 32 % of the phenotypic variation. The most significantly associated SNP was converted to a KASP marker. Additionally, nine minor SnTox3 sensitivity QTL were identified on chromosomes 1B, 2A, 2B, 3B, 4D, 6A, 6B, and 7B, each accounting for 2.6-6.0 % of the phenotypic variation. 2. Gene expression analysis: combining RNA-seq and genomic analysis in a time-course experiment using a SnTox3 sensitive (Cadenza) and insensitive variety (Avalon), two treatments (+/- SnTox3 infiltration) and 0, 4, 8, 12, and 24 hour time-points allowed investigation of gene expression before and after SnTox3 infiltration. Two Snn3-B1 candidate genes were identified, a protein kinase and wall-associated kinase, with analysis of genome-wide patterns of gene expression providing insights into the molecular mechanism of the SnTox3-Snn3-B1 pathway. 3. Adult plant resistance: The Avalon x Cadenza bi-parental population was used to investigate adult plant P. nodorum resistance. First, an improved Avalon x Cadenza genetic map was developed using publicly available genotype data. This was combined with field trial data to identify a major QTL on chromosome 5A for leaf and glume blotch and a further seven QTL on chromosomes 1B, 2D, 3B, 5A, 5B and 7B. Of these, field resistance QTL were found to co-locate with the effector sensitivity QTL Snn1 and Snn7. Collectively, this research provides wheat breeders and researchers with knowledge and molecular resources regarding sensitivity to the P. nodorum effector, SnTox3, as well as field QTL for both leaf and glume blotch.BBSR

Conception et test des circuits et systèmes numériques à haute fiabilité et sécurité

Research activities I carried on after my nomination as Chargé de Recherche deal with the definition of methodologies and tools for the design, the test and the reliability of secure digital circuits and trustworthy manufacturing. More recently, we have started a new research activity on the test of 3D stacked Integrated CIrcuits, based on the use of Through Silicon Vias. Moreover, thanks to the relationships I have maintained after my post-doc in Italy, I have kept on cooperating with Politecnico di Torino on the topics related to test and reliability of memories and microprocessors.Secure and Trusted DevicesSecurity is a critical part of information and communication technologies and it is the necessary basis for obtaining confidentiality, authentication, and integrity of data. The importance of security is confirmed by the extremely high growth of the smart-card market in the last 20 years. It is reported in "Le monde Informatique" in the article "Computer Crime and Security Survey" in 2007 that financial losses due to attacks on "secure objects" in the digital world are greater than $11 Billions. Since the race among developers of these secure devices and attackers accelerates, also due to the heterogeneity of new systems and their number, the improvement of the resistance of such components becomes today’s major challenge.Concerning all the possible security threats, the vulnerability of electronic devices that implement cryptography functions (including smart cards, electronic passports) has become the Achille’s heel in the last decade. Indeed, even though recent crypto-algorithms have been proven resistant to cryptanalysis, certain fraudulent manipulations on the hardware implementing such algorithms can allow extracting confidential information. So-called Side-Channel Attacks have been the first type of attacks that target the physical device. They are based on information gathered from the physical implementation of a cryptosystem. For instance, by correlating the power consumed and the data manipulated by the device, it is possible to discover the secret encryption key. Nevertheless, this point is widely addressed and integrated circuit (IC) manufacturers have already developed different kinds of countermeasures.More recently, new threats have menaced secure devices and the security of the manufacturing process. A first issue is the trustworthiness of the manufacturing process. From one side, secure devices must assure a very high production quality in order not to leak confidential information due to a malfunctioning of the device. Therefore, possible defects due to manufacturing imperfections must be detected. This requires high-quality test procedures that rely on the use of test features that increases the controllability and the observability of inner points of the circuit. Unfortunately, this is harmful from a security point of view, and therefore the access to these test features must be protected from unauthorized users. Another harm is related to the possibility for an untrusted manufacturer to do malicious alterations to the design (for instance to bypass or to disable the security fence of the system). Nowadays, many steps of the production cycle of a circuit are outsourced. For economic reasons, the manufacturing process is often carried out by foundries located in foreign countries. The threat brought by so-called Hardware Trojan Horses, which was long considered theoretical, begins to materialize.A second issue is the hazard of faults that can appear during the circuit’s lifetime and that may affect the circuit behavior by way of soft errors or deliberate manipulations, called Fault Attacks. They can be based on the intentional modification of the circuit’s environment (e.g., applying extreme temperature, exposing the IC to radiation, X-rays, ultra-violet or visible light, or tampering with clock frequency) in such a way that the function implemented by the device generates an erroneous result. The attacker can discover secret information by comparing the erroneous result with the correct one. In-the-field detection of any failing behavior is therefore of prime interest for taking further action, such as discontinuing operation or triggering an alarm. In addition, today’s smart cards use 90nm technology and according to the various suppliers of chip, 65nm technology will be effective on the horizon 2013-2014. Since the energy required to force a transistor to switch is reduced for these new technologies, next-generation secure systems will become even more sensitive to various classes of fault attacks.Based on these considerations, within the group I work with, we have proposed new methods, architectures and tools to solve the following problems:• Test of secure devices: unfortunately, classical techniques for digital circuit testing cannot be easily used in this context. Indeed, classical testing solutions are based on the use of Design-For-Testability techniques that add hardware components to the circuit, aiming to provide full controllability and observability of internal states. Because crypto‐ processors and others cores in a secure system must pass through high‐quality test procedures to ensure that data are correctly processed, testing of crypto chips faces a dilemma. In fact design‐for‐testability schemes want to provide high controllability and observability of the device while security wants minimal controllability and observability in order to hide the secret. We have therefore proposed, form one side, the use of enhanced scan-based test techniques that exploit compaction schemes to reduce the observability of internal information while preserving the high level of testability. From the other side, we have proposed the use of Built-In Self-Test for such devices in order to avoid scan chain based test.• Reliability of secure devices: we proposed an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost.• Fault Attacks: one of the most powerful types of attack for secure devices is based on the intentional injection of faults (for instance by using a laser beam) into the system while an encryption occurs. By comparing the outputs of the circuits with and without the injection of the fault, it is possible to identify the secret key. To face this problem we have analyzed how to use error detection and correction codes as counter measure against this type of attack, and we have proposed a new code-based architecture. Moreover, we have proposed a bulk built-in current-sensor that allows detecting the presence of undesired current in the substrate of the CMOS device.• Fault simulation: to evaluate the effectiveness of countermeasures against fault attacks, we developed an open source fault simulator able to perform fault simulation for the most classical fault models as well as user-defined electrical level fault models, to accurately model the effect of laser injections on CMOS circuits.• Side-Channel attacks: they exploit physical data-related information leaking from the device (e.g. current consumption or electro-magnetic emission). One of the most intensively studied attacks is the Differential Power Analysis (DPA) that relies on the observation of the chip power fluctuations during data processing. I studied this type of attack in order to evaluate the influence of the countermeasures against fault attack on the power consumption of the device. Indeed, the introduction of countermeasures for one type of attack could lead to the insertion of some circuitry whose power consumption is related to the secret key, thus allowing another type of attack more easily. We have developed a flexible integrated simulation-based environment that allows validating a digital circuit when the device is attacked by means of this attack. All architectures we designed have been validated through this tool. Moreover, we developed a methodology that allows to drastically reduce the time required to validate countermeasures against this type of attack.TSV- based 3D Stacked Integrated Circuits TestThe stacking process of integrated circuits using TSVs (Through Silicon Via) is a promising technology that keeps the development of the integration more than Moore’s law, where TSVs enable to tightly integrate various dies in a 3D fashion. Nevertheless, 3D integrated circuits present many test challenges including the test at different levels of the 3D fabrication process: pre-, mid-, and post- bond tests. Pre-bond test targets the individual dies at wafer level, by testing not only classical logic (digital logic, IOs, RAM, etc) but also unbounded TSVs. Mid-bond test targets the test of partially assembled 3D stacks, whereas finally post-bond test targets the final circuit.The activities carried out within this topic cover 2 main issues:• Pre-bond test of TSVs: the electrical model of a TSV buried within the substrate of a CMOS circuit is a capacitance connected to ground (when the substrate is connected to ground). The main assumption is that a defect may affect the value of that capacitance. By measuring the variation of the capacitance’s value it is possible to check whether the TSV is correctly fabricated or not. We have proposed a method to measure the value of the capacitance based on the charge/ discharge delay of the RC network containing the TSV.• Test infrastructures for 3D stacked Integrated Circuits: testing a die before stacking to another die introduces the problem of a dynamic test infrastructure, where test data must be routed to a specific die based on the reached fabrication step. New solutions are proposed in literature that allow reconfiguring the test paths within the circuit, based on on-the-fly requirements. We have started working on an extension of the IEEE P1687 test standard that makes use of an automatic die-detection based on pull-up resistors.Memory and Microprocessor Test and ReliabilityThanks to device shrinking and miniaturization of fabrication technology, performances of microprocessors and of memories have grown of more than 5 magnitude order in the last 30 years. With this technology trend, it is necessary to face new problems and challenges, such as reliability, transient errors, variability and aging.In the last five years I’ve worked in cooperation with the Testgroup of Politecnico di Torino (Italy) to propose a new method to on-line validate the correctness of the program execution of a microprocessor. The main idea is to monitor a small set of control signals of the processors in order to identify incorrect activation sequences. This approach can detect both permanent and transient errors of the internal logic of the processor.Concerning the test of memories, we have proposed a new approach to automatically generate test programs starting from a functional description of the possible faults in the memory.Moreover, we proposed a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success