A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level

A 1 GS/s, 31 MHz BW, 76.3 dB Dynamic Range, 34 mW CT-ΔΣ ADC with 1.5 Cycle Quantizer Delay and Improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- ΔΣ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results

Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog) domain into utilizing charge or time as the variable that can be processed by mostly digital/passive circuits. In this thesis, both circuit-level techniques and architectures are proposed that are inherently compatible with transistor scaling in submicron CMOS, meanwhile achieving state-of-the-art performance and optimizing power efficiency. The first part focuses on a highly reconfigurable charge-domain switched-g[subscript m]-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge sharing technique. It uses only switches, capacitors, linearity-enhanced gm-stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and -3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two proposed biquads in a 65nm LPE CMOS process. A tunable center frequency of 35−70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies a core area of 0.17mm². In the second part, a highly linear continuous-time low-pass filter (LPF) topology with source follower coupling is presented that achieves excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two proposed filter stages in a 0.18μm CMOS, and occupies a core area of 0.12mm². Operating with a 1.3V supply voltage, the filter consumes only 0.5mA current, and achieves a -3dB bandwidth of 20MHz with 82dB stop-band rejection. A total harmonic distortion (THD) of -39.5dB at the output is measured with a +6.6dBm (i.e. 1.35V[subscript pk-pk]) input signal at 2MHz. The measured in-band IIP3 is +28.8dBm. The dynamic range (at 1% THD) is 76.8dB, with 15.3nV/√Hz averaged in-band input-referred noise. A pseudo-differential-VCO based 2nd-order continuous-time ΔΣ ADC with a residue self-coupling technique is proposed and implemented with mostly digital circuits in the third part. Two VCOs are arranged in a pseudo-differential manner. The digital output is obtained by comparing the sampled output phase of one VCO with that of the other. Passive subtraction is realized in current domain to obtain the residue at the VCO input. The residue self-coupling is implemented using a linear 1st-order transconductance low-pass filter (TCLPF). Moreover, a highly linear VCO topology is presented. The transistor-level simulations in a 65nm CMOS process show a 78dB SNDR over a 10MHz signal bandwidth with a power consumption of 2.9mW, which is 16dB improvement in contrast to the case with the TCLPF block powered off

Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution

Contribución a la ecualización de señal en sensores basados en modulación SIGMA-DELTA

El trabajo de investigación de esta tesis doctoral consiste en obtener una arquitectura de Convertidor Analógico-Digital (ADC) que sea capaz de procesar señales en dos bandas de frecuencias diferentes (tanto en la banda de audio como en la banda de ultrasonidos) de la manera más eficiente posible en consumo de potencia y área. Implementar un nuevo ADC que permita esta funcionalidad es costoso y requeriría el diseño desde el inicio de todos los componentes que lo forman, por lo que, como alternativa, se propone realizar la modificación de un ADC previamente diseñado e integrado con un micrófono digital para su uso en aplicaciones de ultrasonidos. Este ADC esta optimizado para su funcionamiento en la banda de audio por lo que no cumpliría las especificaciones necesarias para la banda de ultrasonidos, siendo necesario variar su comportamiento en dicha banda, sin alterar su comportamiento en la banda de audio. Tras estudiar diferentes técnicas que permiten la modificación del ADC, la opción más eficiente consiste en amplificar la señal en la banda de ultrasonidos mediante la adición de una serie de coeficientes feedforward. Estos coeficientes modifican la función de transferencia de la señal sin afectar al ruido del ADC. Una vez propuesta la técnica que permite procesar señales en ambas bandas de frecuencia, se realizan una serie de estudios teóricos para analizar cuál es el impacto de dicha técnica en el ADC, en términos de estabilidad, linealidad y consumo de potencia. La obtención de los coeficientes feedforward necesarios para obtener una determinada mejora en la banda de ultrasonidos del ADC no es una tarea sencilla, por lo que en esta tesis se ha diseñado una herramienta que permite ayudar en el diseño de estos coeficientes de manera que se pueda conseguir la especificación requerida. Esta herramienta consta de diferentes fases en las que se realizan una serie de cálculos teóricos y simulaciones hasta la obtención de los valores de los nuevos coeficientes feedforward. Finalmente, la técnica propuesta ha sido evaluada mediante un caso práctico de aplicación a un ADC de tercer orden implementado para un micrófono digital. Este ADC ha sido modificado de manera que puede ser empleado tanto para audio como para ultrasonidos, aprovechando la respuesta en frecuencia del sensor MEMS, con una adición de hardware mínima, tan solo un condensador y dos interruptores. La técnica de ecualización se ha combinado con otras técnicas adicionales que han permitido su aplicación practica a nivel de circuito.The research work of this doctoral thesis consists of getting an architecture of Analogto- Digital Converter (ADC) that is able to process signals in two different frequency bands (the audio band and the ultrasound band) in an effective way in terms of power consumption and area. Implementing a new ADC that allows this functionality is expensive and requires the design from the start of all its components. For this reason, this thesis proposes, as an alternative, to modify an ADC previously designed and integrated with a digital microphone to use it in ultrasound applications. This ADC is optimized for its operation in the audio band, not satisfying the specifications needed for the ultrasound band. It is necessary to vary its behavior in the ultrasound band without changing its behavior in the audio band. After studying different techniques that allow the modification of the ADC, the most efficient option consists of amplifying the signal in the ultrasound band adding some feedforward coefficients. These coefficients modify the signal transfer function without affecting the noise of the ADC. Once proposed the technique that allows to process signals in both frequency bands, some theoretical studies are realized to analyze which is the impact of the technique in the ADC in terms of stability, linearity and power consumption. Obtaining the feedforward coefficients needed to reach a certain improvement in the ultrasound band of the ADC is not an easy task, so that in this thesis a toll has been designed for helping in the design of the coefficients to reach the required specification. This tool consists of different phases in which some theoretical calculations and simulations have been realized until obtaining the values of the new feedforward coefficients. Finally, the proposed technique has been evaluated through a practical case of application to a third order ADC, initially implemented for audio applications. This ADC has been modified so that it can be used for both audio and ultrasound applications, taking advantage the MEMS frequency response, with the minimum hardware addition, only a capacitor and two switches. This equalization technique has been combined with other additional techniques that allow its practical application at circuit level.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Emilio Olías Ruiz.- Secretario: Rocío del Río Fernández.- Vocal: Francisco Colodro Rui