A survey of energy saving techniques for mobile computers

Portable products such as pagers, cordless and digital cellular telephones, personal audio equipment, and laptop computers are increasingly being used. Because these applications are battery powered, reducing power consumption is vital. In this report we first give a survey of techniques for accomplishing energy reduction on the hardware level such as: low voltage components, use of sleep or idle modes, dynamic control of the processor clock frequency, clocking regions, and disabling unused peripherals. System- design techniques include minimizing external accesses, minimizing logic state transitions, and system partitioning using application-specific coprocessors. Then we review energy reduction techniques in the design of operating systems, including communication protocols, caching, scheduling and QoS management. Finally, we give an overview of policies to optimize the code of the application for energy consumption and make it aware of power management functions. Applications play a critical role in the user's experience of a power-managed system. Therefore, the application and the operating system must allow a user to control the power management. Remarkably, it appears that some energy preserving techniques not only lead to a reduced energy consumption, but also to more performance

Automatic Standby Power-Saving Power Strip

The Standby Power Saving Power Strip improves on common power strip functionality. The project reduces the power loss from most electrical devices’ standby power mode, while retaining the convenience of leaving the devices plugged-in. The surge protector automatically recognizes when the plugged-in devices enter standby power mode. Then, it shuts off power to that device and automatically provides power back to the plugged-in devices, when turned on

5 Watt GaN HEMT Power Amplifier for LTE

This work presents the design and implementation of a stand-alone linear power amplifier at 2.4 GHz with high output power. A GaN HEMT transistor is selected for the design and implementation of the power amplifier. The device exhibits a gain of 11.7 dB and a drain efficiency of 39% for an output power of 36.7 dBm at 2.4 GHz for an input power of 25dBm. The carrier to intermodulation ratio is better than 25 dB for a two tone input signal of 25 dBm of total power and a spacing of 5 MHz. The fabricated device is also tested with LTE input signals of different bandwidths (5MHz to 20MHz)

Switched-Capacitor 2:1 Step-Down Voltage Converter Modulated on 90nm and 45nm

DC-DC converters are one of the main component of a power management unit. Their main role is to provide a constant, smooth output voltage to power the electronic devices. Switching mode DC-DC converters are critical building blocks in portable devices such as mobile phones, laptop, etc and hence their  efficiency and power are a important issue. This paper describes design techniques to maximize the efficiency of switched-capacitor (SC) DC-DC converters. The measured performance of  switched capacitor converter implemented on tanner EDA tool at 45 nm and 90nm CMOS technology with 2V input voltage to support  efficiency 94-95% Keywords: DC-DC conversion, switched-capacitor, switching converte

TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets

This brief introduces Topology Voltage Frequency Scaling (TVFS), a performance management technique for embedded Convolutional Neural Networks (ConvNets) deployed on low-power CPUs. Using TVFS, pre-trained ConvNets can be efficiently processed over a continuous stream of data, enabling reliable and predictable multi-inference tasks under latency constraints. Experimental results, collected from an image classification task built with MobileNet-v1 and ported into an ARM Cortex-A15 core, reveal TVFS holds fast and continuous inference (from few runs, up to 2000), ensuring a limited accuracy loss (from 0.9% to 3.1%), and better thermal profiles (average temperature 16.4 °C below the on-chip critical threshold)

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections