Benini, Luca

Kremer, Uli

Probst, Christian

Schelkens, Peter

Online Research Database In Technology

Power-aware Computing SystemsDagstuhl Seminar 05141April 3rd to April 8th 2005Luca Benini1, Uli Kremer2, Christian W. Probst3, and Peter Schelkens41 Universita di Bologna, DEISViale Risorgimento 2, 40136 Bologna, Italylbenini@deis.unibo.it2 Rutgers University, Dept.of Computer Science96 Frelinghuysen Road, NJ 08854 Piscataway, USAuli@cs.rutgers.edu3 Technical University of Denmark, Informatics and Mathematical ModellingRichard Petersens Plads, 2800 Kongens Lyngby, Denmarkprobst@imm.dtu.dk4 Vrije Universiteit Brussel, Dept. of Electronics and Information Processing (ETRO)Pleinlaan 2, 1050 Brussel, BelgiumPeter.Schelkens@vub.ac.beAbstract. This paper summarizes the objectives and structure of a sem-inar with the same title, held from April 3rd to April 8th 2005 at SchlossDagstuhl, Germany.1 IntroductionRapidly increasing chip densities and processor speeds have made energy dis-sipation a leading concern in computer design. The problem raised by energyconsumption is especially severe for a whole class of computing devices whichhas recently become almost ubiquitously available|mobile devices like note-books, PDAs, or mobile phones. On the one hand, these are only equipped witha very limited power supply, so any computation on such a device should beespecially careful about resource usage. Even worse, the battery technology forthese devices has not kept pace with advances in processor technology and thegrowing complexity of software. On the other hand, cooling mechanisms becomemore and more important. Recent trends suggest that processor power consump-tion doubles every four years|and cooling costs rise exponentially with heatincreases [1]. The future processors will require energy management solutionsmore cost eective than the cooling fans used today.It has been the goal of the seminar to bring together researchers from themain communities working on reducing power consumption, namely hardware,operating systems, virtual-execution environments, compilers, and applications.The main seminar result, given in Section 3, is a classication of the obstacles,2 L. Benini, U. Kremer, C.W. Probst, P. Schelkensand therefore research directions, with respect to power consumption seen fordierent classes of devices, ranging from very low power devices, over handhelddevices, to servers and work stations. In a next step the seminar identied theimpact dierent levels of dealing with power concerns can have.2 Approaches to Reduce Energy ConsumptionFigure 1 gives an overview of the dierent levels that energy saving techniquescan be applied at and some of the techniques available. It is noteworthy thatleakage is rapidly becoming the dominant source of power consumption.On the hardware level, decisions inuence how software will be able to aectpower dissipation. Similarly, decisions on the software level, that is operatingsystem, compiler, virtual-execution environment, or application level, inuencethe processor's workload. Developing an integrated approach remains an openproblem, although a number of research groups have started to explore it. How-ever, currently most research is done in a vacuum, making assumptions aboutthe execution environment that do not take into account the eect of othertechniques.Low-power computing is challenging rst of all due to the sheer explosionof total hardware/software decisions [2]. The problem is further complicatedby decisions along any dimension having tradeos along other dimensions. Onetradeo is between power and performance. Another is that minimizing powermight introduce sharp power variations that impair chip reliability.The third reason low power design is nontrivial is that no decision exists ina vacuum. A compiler can emit code to slow down the processor during memorystalls, but an operating system can override the compiler's decision by speed-ing up the processor at the same time. Without synergy between the compilerRemote ExecutionFidelity ReductionResource HybernationAlgorithm Design SchedulingMemory ManagementEnergy AccountingTechniquesLeakage ReductionHardwareSoftwareClassificationApplicationVirtual MachineCompilerOperating SystemArchitectureGatesTransistors Transistor Sizing Transistor OrderingGate RestructuringTechnology MappingClock, Memory, and Interconnect OptimizationsFig. 1. An overview of techniques to achieve energy savings at dierent levels.The left hand part lists levels of hard- on software, the right hand part exemplarytechniques that are applicable at that level.Power-aware Computing Systems 3and operating system, frequency thrashing can occur, resulting in power andperformance degradation. More generally, without synergy among decisions atdierent levels of design, the eect of any power reduction technique will beshort lived.For all of these reasons, the problem of developing an integrated approach topower management remains unsolved, though researchers are addressing powerissues at every level of design.3 Where does the Power go?In a series of discussion sessions the seminar participants tried to identify wherepower is consumed in devices. This resulted in a matrix (Figure 2) that ranks howmuch dierent areas (Computation, Communication and I/O, Storage, Other)of dierent classes of systems (Very Low Power, Systems on a Chip, GeneralPurpose Computing) contribute to the total system power consumption.This matrix was then used to identify the impact that we expect dierentlevels to have, as well as techniques provided by and problems to be solved ineach of the levels. The levels considered are{ Logic, Circuit, and Technology,{ Architectures and Micro-Architectures,CommunicationStorageI/OComputation Other2 3General ServerDRAM/DISK3 1Power SupplyPurposeWork 1 1ComputingStation2WLAN/LCD GPU/CPU3Receive 2 1 1 -SoC for1 2Digital Duplex 3RF/LCD CPU-Conver-no Commu- 2gencenication1 1specialized HW-2Very Low Power may be 1 for 1 3 -non-RF hardwareFig. 2. Contribution of dierent areas to the power consumption of classes ofdevices, ranging from very low power devices like sensors, over hand-held devices,to work stations and servers. The areas are sorted according to their importancefrom 1 (most important) to 3 (least important).4 L. Benini, U. Kremer, C.W. Probst, P. Schelkens{ Compilers, Virtual-Execution Environments, Operating Systems, and Mid-dleware, and{ Applications and Algorithms.The following sections give an overview of the results identied in working groupsfor the respective levels.3.1 Logic, Circuit, and TechnologyOn the hardware level leakage power has been identied as the major problem.In scaling for performance, the main goal is to reduce both supply voltage as wellas gate threshold voltage to reduce dynamic power, while keeping enough drivecurrent. Unfortunately, that creates an exponential rise in leakage power thateven can exceed dynamic power|that is, the energy used without the systemdoing anything is higher than the energy used for the actual operation.One solution would be to increase the gate threshold voltage, which resultsin lower leakage power, but also shrinks the acceptable range of supply voltage.To compensate for this, one would need ever thinner gate oxides|which resultsin increased gate leakage.So using current technologies, scaling as usual will not do the trick. At thesame time new device architectures are needed. However, since Moore's law stillseems to be valid, choices will have to be made rather quickly, identifying theright technology to create cost eective yielding processes that will be usable ingiga-scale architectures.The ITRS roadmap [3] requests that the increase in overall power consump-tion should be almost zero in this decade, while dynamic power alone currentlyincreases 1.4 times per 3 years. If the leakage component is added to thesenumbers, the increase becomes much steeper. Thus the power increase mightbecome a big stumbling block to Moores law. At the same time, frequency, sup-ply voltage, and threshold-voltage selection heavily depend on the workload andcan thus require interaction with the system level. Hardware, however, severelylimits the degrees of freedom available, and beyond 65nm technology both leak-ing as well as gate delay get out of hand, unless the size of devices is increased,counteracting the idea of scaling. Clearly a fundamental change in CMOS devicearchitecture is needed to keep up the pace of Moore's law.From the perspective of the logic, circuit, and technology level it is question-able whether more parallelism is going to reduce the overall energy consump-tion. While extra parallelism allows to reduce the supply voltage for the sameperformance and in this way to reduce power/energy, it also introduces extratransistors (more leakage) and extra and longer wires (more capacitive coupling,noise issues). On top of these issues a lower supply voltage also stresses the vari-ability issues. To be able to resolve these problems we need to better understandthe underlying physical phenomena. This will require more interaction betweenthe system/architecture, circuits, and technology communities.Power-aware Computing Systems 53.2 Architectures and Micro-ArchitecturesThe common trend in (micro-) architecture design is to have numerous small,potentially heterogeneous/special-purpose cores. These architectures are domi-nated by communication across cores. In the general-purpose domain the mainproblem is resource contention that requires intelligent coordination to be re-solved. In the application-specic domain, architectures can be optimized withrespect to power consumption, e.g. by using a simplied voltage-gating approach.In order to allow an energy-ecient usage of a given architecture, it shouldexpose any non-uniformity to allow its exploitation by the software system run-ning on top. Other needs include support for high-bandwidth communicationbetween devices, more explicit support for concurrency, as well as mechanismsto exploit locality. Additionally there is an urgent need to develop APIs and in-struction set architectures that allow systems to express and control variabilityin the architecture and application. This would require a holistic approach thatencompasses I/O, storage, and compute resources.On the other hand, there are topics that can be better dealt with by otherlayers. The level of logic, circuits, and technology should support an energy-aware design and provide power-management knobs that support not only DVS,threshold-power control, supply-power control, and leakage, but also new, yetundiscovered approaches. The compiler, operating system, virtual-execution en-vironment, and middleware layer should leverage the API provided by the ar-chitecture. Finally, at the application layer one would need new programmingmodels to allow the overall system to eciently use the resources provided bythe architecture.The main open issue on the architecture level is parallelism and how toextract it eciently. This might require re-architecting the CPU, storage hier-archies, and more. Increases in parallelism might also call for rethinking thehardware support and hardware/software coordination regarding task schedul-ing, placement, and migration.3.3 Compilers, Virtual-Execution Environment, Operating Systemsand MiddlewareThe layer of compilers, virtual-execution environments, operating systems, andmiddleware is especially well suited to predict and determine the current and fu-ture behavior of programs and tasks by using just-in-time compilation to reshapeprogram behavior at run time. Components on this level can pass informationup and down to lower and higher levels, e.g. to disable memory banks in com-putation intensive areas of an application.In general, these components could process implicit and explicit application-level constraints, e.g. related to security, reliability, and real time. However, thisis a mechanism that is mostly unsupported by current programming models. Toallow systems and programmers to benet from constraint processing we wouldneed new power-aware programming models.6 L. Benini, U. Kremer, C.W. Probst, P. SchelkensAs a rule of thumb one can say that the higher the overhead of an opti-mization or analysis, the coarser granularity is needed to make it work, that isto justify the need to enable it. This leads to the question which optimizationsare most protable for the reduction of energy consumption. The working groupidentied hibernation of resources to reduce leakage, DVS of whole processorsand individual cores, and quality of result tradeos, where the last one wouldrequire semantic models to allow the quantication of tradeos. The most prof-itable optimizations and analyses to enable decisions on how to adjust systemparameters are parallelization, phase detection (e.g. ag change in communica-tion requirements), and pattern detection (e.g. producer/consumer). Especiallythe detection of phases and patterns would allow to adjust the overall systemparameters according to the current system role.The challenge in the area of compilers, virtual-execution environments, oper-ating systems, and middleware is to dene and enable interactions across dier-ent layers. By systematically designing all layers of complete systems, each layercan be designed such that it can make assumptions on the behavior of otherlayers and will be able to inuence the overall system behavior. The ultimategoal is to develop a whole-system solution that can deal with the variability ofthe resource requirements and execution constraints of the application as wellas of the features and resources of the target system.3.4 Applications and AlgorithmsGenerally speaking the optimization potential increases with the abstractionlevel, making it advantageous to optimize at the system and algorithmic level.There are two possible approaches to enable those optimizations|either by ac-quiring application knowledge or by developing domain-specic systems andalgorithmic-evaluation frameworks.Evaluation frameworks need to support scenarios that reect the huge sys-tem space in a representative way to reduce the time needed for simulation ofthe system behavior. The main property required in these frameworks is thatthey oer domain-specic architectural templates that include and model allsystem components to allow substantiated simulation results. In addition, eachsystem component needs to be equipped with a power model that is as accurateas possible. Currently these models are often hard to obtain from industry oreven unavailable, e.g. for some analogue components whose behavior is hard todescribe.Having these general evaluation frameworks available would allow to identifythe critical consumers in a system design. These would then be targeted to reducetheir power consumption. To support this process, metrics for the tradeo areneeded. For example in multimedia applications a technique to measure or judgethe picture quality per consumed Watt would be needed.In the area of applications and algorithms this working group identied twomajor challenges. To enable evaluation frameworks we will need domain-specicpower-optimization technologies that cover the system and implementation lev-Power-aware Computing Systems 7els. In addition we need an interdisciplinary engineering approach to co-designthe hardware, software, and applications of power-aware computing systems.4 The SeminarThe program of the seminar featured presentations of about 35 participatingresearchers from academia and industry. They were chosen to represent majorareas in targeting the energy consumption of a computing system|Applications,Compilers, Virtual-execution Environments, Operating Systems, and Hardware.In order to identify problem areas and future research areas, discussion groupswere formed that resulted in four working groups whose results are presentedin this report. In addition, abstracts of the presentations as well as work-in-progress papers are published in these proceedings. Some of the work presentedat the seminar will be published in a special issue of the International Journalof Embedded Systems on power, energy, and thermal topics.References1. Gunther, S.H., Binns, F., Carmean, D.M., Hall, J.C.: Managing the Impact ofIncreasing Microprocessor Power Consumption. Intel Technology Journal (2001)Q1 issue.2. Venkatachalam, V., Franz, M.: Power Reduction Techniques for MicroprocessorSystems. Accepted for publication in ACM Computing Surveys (2005)3. ITRS: The International Technology Roadmap for Semiconductors, available athttp://public.itrs.net (2004)

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