ARCHITECTURE DESIGN AND IMPLEMENTATION OF THE INCREASING RADIUS - LIST SPHERE DETECTOR ALGORITHM

A list sphere detector (LSD) is an enhancement of a sphere detector (SD) that can be used to approximate the optimal MAP detector. In this paper, we introduce a novel architecture for the increasing radius (IR)-LSD algorithm, which is based on the Dijkstra’s algorithm. The parallelism possibilities are introduced in the presented architecture, which is also scalable for different multiple-input multiple-output (MIMO) systems. The novel architecture is implemented on a Virtex-IV field programmable gate array (FPGA) chip using high-level ANSI C++ language based Catapult C Synthesis tool from Mentor Graphics. The used word lengths, the latency of the design, and the required resources are presented and analyzed for 4 x 4 MIMO system with 16- quadrature amplitude modulation (QAM). The detector implementation achieves a maximum throughput of 12.1Mbps at high signal-to-noise ratio (SNR)

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage of the trellis maps to a possible complex-valued symbol transmitted by antenna. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4x4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology.With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps.With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps

Implementation of a High Throughput Soft MIMO Detector on GPU

Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver. To extract maximum performance from a MIMO system, a computationally intensive search based detector is needed. To meet the challenge of MIMO detection, typical suboptimal MIMO detectors are ASIC or FPGA designs. We aim to show that a MIMO detector on Graphic processor unit (GPU), a low-cost parallel programmable co-processor, can achieve high throughput and can serve as an alternative to ASIC/FPGA designs. However, careful architecture aware software design is needed to leverage the performance offered by GPU. We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGA-like performance and handle different configurations in software on GPU. The proposed design can be used to accelerate wireless physical layer simulations and to offload MIMO detection processing in wireless testbed platforms.NokiaNokia Siemens Networks (NSN)Texas InstrumentsXilinxNational Science Foundatio

Técnicas de precodificación lineal para coordinación de celdas en sistemas MIMO

En sistemas multiantena y multiusuario MU-MIMO (Multi-user Multiple-Input Multiple-Output), la multiplexación espacial puede aumentar la tasa de bit sin necesidad de implementar costosos sistemas de procesado de señal. Ya sea a corto o largo plazo, la información de canal estará disponible en las estaciones base BTS (Base Station) siendo posible la precodificación coordinada de las señales deseadas por los usuarios. Esta precodificación se puede usar de forma muy eficiente para eliminar la interferencia multiusuario MUI (Multi-User Interference) usando Codificación en Papel Sucio, del inglés, “Dirty Paper Coding” (DPC) o Técnicas de Precodificación Lineal. Estas técnicas permiten que el procesamiento complejo se realice en la estación base, simplificando de manera significativa los terminales móviles de los usuarios. A lo largo del proyecto se estudiarán diferentes técnicas Lineales de Precodificación de canal sobre un escenario MU-MIMO con reuso universal de frecuencia (UFR). Se utiliza un modelo de sistema realista en espacio y se asume el conocimiento a priori del canal. _______________________________________________________________________________________________________________In Multi-User Multiple-Input Multiple-Output (MU-MIMO) systems, spatial multiplexing can be employed to increase the throughput without the need of expensive signal processing technologies. In the case that channel state information is available at the base station (BTS), this will facilitate the joint precoding of the signals intended for the different users. Precoding is used to efficiently eliminate or suppress Multi-User Interference (MUI) via Linear Precoding Techniques or by using “Dirty Paper Coding” (DPC). It also allows us to perform most of the complex processing at the BTS which leads to a simplification of the mobile terminals. In this document, we will study different Linear Precoding Techniques in MU-MIMO systems using universal frequency reuse (UFR). We will work with a realistic spatial system and we will assume the a priori knowledge of channel.Ingeniería Técnica en Sistemas de Telecomunicació

On the application of graphics processor to wireless receiver design

In many wireless systems, a Turbo decoder is often combined with a soft-output multiple-input and multiple-output (MIMO) detector at the receiver to maximize performance in many 4G and beyond wireless standards. Although custom application specific designs are usually used to meet this challenge, programmable graphics processing units (GPU) has become an alternative to the traditional ASIC and FPGA solution for wireless applications. However, careful architecture-aware algorithm design and mapping are required to maximize performance of a communication block on GPU. For MIMO soft detection, we implemented a new MIMO soft detection algorithm, multi-pass trellis traversal (MTT). For Turbo decoding, we used a parallel window algorithm. We showed that our implementations can achieve high throughput while maintaining good performance. This work will allow us to implement a complete iterative MIMO receiver in software on GPU in the future

VLSI Implementation of Low Power Reconfigurable MIMO Detector

Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial multiplexing to increase channel bandwidth which requires the use of multiple antennas in the receiver and transmitter side. The increase in bandwidth comes at the cost of high silicon complexity of MIMO detectors which result, due to the intricate algorithms required for the separation of these spatially multiplexed streams. Previous implementations of MIMO detector have mainly dealt with the issue of complexity reduction, latency minimization and throughput enhancement. Although, these detectors have successfully mapped algorithms to relatively simpler circuits but still, latency and throughput of these systems need further improvements to meet standard requirements. Additionally, most of these implementations don’t deal with the requirements of reconfigurability of the detector to multiple modulation schemes and different antennae configurations. This necessary requirement provides another dimension to the implementation of MIMO detector and adds to the implementation complexity. This thesis focuses on the efficient VLSI implementation of the MIMO detector with an emphasis on performance and re-configurability to different modulation schemes. MIMO decoding in our detector is based on the fixed sphere decoding algorithm which has been simplified for an effective VLSI implementation without considerably degrading the near optimal bit error rate performance. The regularity of the architecture makes it suitable for a highly parallel and pipelined implementation. The decoder has intrinsic traits for dynamic re-configurability to different modulation and encoding schemes. This detector architecture can be easily tuned for high/low performance requirements with slight degradation/improvement in Bit Error Rate (BER) depending on needs of the overlying application. Additionally, various architectural optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage and frequency scaling have been explored to improve the performance, energy requirements and re-configurability of the design

Scalable System Design for Covert MIMO Communications

In modern communication systems, bandwidth is a limited commodity. Bandwidth efficient systems are needed to meet the demands of the ever-increasing amount of data that users share. Of particular interest is the U.S. Military, where high-resolution pictures and video are used and shared. In these environments, covert communications are necessary while still providing high data rates. The promise of multi-antenna systems providing higher data rates has been shown on a small scale, but limitations in hardware prevent large systems from being implemented