Multiple Input Multiple Output (MIMO) systems are a key technology for next
generation high speed wireless communication standards like 802.11n, WiMax etc.
MIMO enables spatial multiplexing to increase channel bandwidth which requires the
use of multiple antennas in the receiver and transmitter side. The increase in bandwidth
comes at the cost of high silicon complexity of MIMO detectors which result, due to the
intricate algorithms required for the separation of these spatially multiplexed streams.
Previous implementations of MIMO detector have mainly dealt with the issue of
complexity reduction, latency minimization and throughput enhancement. Although,
these detectors have successfully mapped algorithms to relatively simpler circuits but
still, latency and throughput of these systems need further improvements to meet
standard requirements. Additionally, most of these implementations don’t deal with the
requirements of reconfigurability of the detector to multiple modulation schemes and
different antennae configurations. This necessary requirement provides another
dimension to the implementation of MIMO detector and adds to the implementation
complexity.
This thesis focuses on the efficient VLSI implementation of the MIMO detector
with an emphasis on performance and re-configurability to different modulation
schemes. MIMO decoding in our detector is based on the fixed sphere decoding
algorithm which has been simplified for an effective VLSI implementation without
considerably degrading the near optimal bit error rate performance. The regularity of the
architecture makes it suitable for a highly parallel and pipelined implementation. The
decoder has intrinsic traits for dynamic re-configurability to different modulation and
encoding schemes. This detector architecture can be easily tuned for high/low
performance requirements with slight degradation/improvement in Bit Error Rate (BER)
depending on needs of the overlying application. Additionally, various architectural
optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage
and frequency scaling have been explored to improve the performance, energy
requirements and re-configurability of the design
