Low power test compatibility classes: exploiting regularity for simultaneous reduction in test application time and power dissipation

Traditional DFT methodologies increase useless power dissipation during testing and are not suitable for testing low power VLSI circuits leading to lower reliability and manufacturing yield. Traditional test scheduling approaches based on fixed test resource allocation decrease power dissipation at the expense of higher test application time. On the one hand it was shown that power conscious test synthesis and scheduling eliminate useless power dissipation. On the other hand by exploiting regularity in BIST RTL data paths using test compatibility classes an improvement in test application time, BIST area overhead, performance degradation, volume of test data, and fault escape probability is achieved. This paper shows that when combining power conscious test synthesis and scheduling with the test compatibility classes into low power test compatibility classes, simultaneous reduction in test application time and power dissipation is obtained

Evaluation of a Liquid Amine System for Spacecraft Carbon Dioxide Control

The analytical and experimental studies are described which were directed toward the acquisition of basic information on utilizing a liquid amine sorbent for in use in a CO2 removal system for manned spacecraft. Liquid amine systems are successfully used on submarines for control of CO2 generated by the crew, but liquid amines were not previously considered for spacecraft applications due to lack of development of satisfactory rotary phase separators. Developments in this area now make consideration of liquid amines practical for spacecraft system CO2 removal. The following major tasks were performed to evaluate liquid amine systems for spacecraft: (1) characterization, through testing, of the basic physical and thermodynamic properties of the amine solution; (2) determination of the dynamic characteristics of a cocurrent flow absorber; and (3) evaluation, synthesis, and selection of a liquid amine system concept oriented toward low power requirements. A low weight, low power system concept was developed. Numerical and graphical data are accompanied by pertinent observations

Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy, is presented. The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power VLSI circuits using built-in self-test (BIST) at RTL. First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, BIST area overhead, performance degradation, volume of test data, fault-escape probability, and complexity of the testable design space exploration. Second, power minimisation in BIST RTL data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Third, the new BIST methodology has been validated using benchmark examples. Further, it is shown that when the proposed power conscious test synthesis and test scheduling is combined with novel test compatibility classes simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time

Constraining the fraction of Compton-thick AGN in the Universe by modelling the diffuse X-ray background spectrum

This paper investigates what constraints can be placed on the fraction of Compton-thick (CT) AGN in the Universe from the modeling of the spectrum of the diffuse X-ray background (XRB). We present a model for the synthesis of the XRB that uses as input a library of AGN X-ray spectra generated by the Monte Carlo simulations described by Brightman & Nandra. This is essential to account for the Compton scattering of X-ray photons in a dense medium and the impact of that process on the spectra of obscured AGN. We identify a small number of input parameters to the XRB synthesis code which encapsulate the minimum level of uncertainty in reconstructing the XRB spectrum. These are the power-law index and high energy cutoff of the intrinsic X-ray spectra of AGN, the level of the reflection component in AGN spectra and the fraction of CT AGN in the Universe. We then map the volume of the space allowed to these parameters by current observations of the XRB spectrum in the range 3-100 keV. One of the least constrained parameters is the fraction of CT AGN. Statistically acceptable fits to the XRB spectrum at the 68% confidence level can be obtained for CT fractions in the range 5-50%. This is because of degeneracies among input parameters to the XRB synthesis code and uncertainties in the modeling of AGN spectra (e.g. reflection). The most promising route for constraining the fraction of CT AGN in the Universe is via the direct detection of those sources in high energy (>10keV) surveys. It is shown that the observed fraction of CT sources identified in the SWIFT/BAT survey, limits the intrinsic fraction of CT AGN, at least at low redshift, to 10-20% (68% confidence level). We also make predictions on the number density of CT sources that current and future X-ray missions are expected to discover. Testing those predictions will constrain the intrinsic fraction of CT AGN as a function of redshift.Comment: To appear in A&

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation

abstract: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation.Dissertation/ThesisMasters Thesis Electrical Engineering 201

High-speed high-resolution low-power self-calibrated digital-to-analog converters

High-speed and high-resolution low-power digital-to-analog converters (DACs) are basic design blocks in many applications. Several obvious conflicting requirements such as high-speed, high-resolution, low-power, and small-area have to be satisfied. In this dissertation, a modular architecture for continuous self-calibrating DACs is proposed to satisfy the above requirements. This includes a redundant-cell-relay continuous self-calibration scheme. Several prototype DACs were implemented with self-calibration schemes. Also a DAC synthesis algorithm using a direct-mapping method and the modular structure was developed and implemented in the Cadence SKILL programming language.;One of the prototypes is a 250MS/s 8-bit continuous self-calibrated DAC that has been implemented in TSMC\u27s 0.25mu single poly five metal logic CMOS process. The structure of the self-calibrated current cell has high impedance and low sensitivity to output node voltage fluctuations. The chip has achieved +0.15/-0.1 LSB DNL, -0.6/+0.4 LSB INL, and 55dB SFDR with a lower input frequency at a conversion rate of 250MS/s. It consumes 8 mW of power in a 0.13 mm2 die area.;Glitches caused by switching of the calibration clock degrade the SFDR especially in high-speed applications. A new redundant-cell-relay continuous self-calibration scheme was proposed to reduce the glitches. Simulation results showed that the glitch energy is reduced 10 fold over existing schemes. A 10-bit DAC was implemented in the 0.25mu CMOS process mentioned above. +/-0.5 LSB INL and -0.45/+0.2 LSB DNL were measured and 70dB SFDR was achieved with a lower input frequency at a 250MS/s conversion rate. Up to the Nyquist rate, the SFDR is above 53dB at a conversion rate of 200MS/s. The DAC dissipates 8mW in a 0.3mm2 die area. The testing results verified the redundant-cell-relay continuous self-calibration for high-speed high-resolution low-power and low-cost DACs.;Additionally, a DAC synthesis algorithm was developed based on a direct mapping method. Given the specifications such as the DAC\u27s resolution, full range scale and technology, the synthesizer will map them directly into pre-existing functional blocks implemented in the DAC synthesis libraries. The program will then synthesize the schematic and layout that closely meet the given specifications

Synthesis of high ion exchange zeolites from coal fly ash

This study focuses on the synthesis at a pilot plant scale of zeolitic material obtained from the coal fly ashes of the Teruel and Narcea power plants in Spain. After the optimisation of the synthesis parameters at laboratory scale, the Teruel and Narcea fly ashes were selected as low and high glass fly ashes. The pilot plant scale experiments were carried out in a 10 m3 reactor of Clariant SA (Barcelona, Spain). The results allowed obtaining 1.1 and 2.2 tonnes of zeolitic material with 40 and 55% of NaP1 content, in two single batch experiments of 24 and 8 hours, for Teruel and Narcea fly ashes, respectively. The cation exchange capacities (CEC) of the final product reached 2.0 and 2.7 meq g-1 for Teruel and Narcea zeolitic material, respectively, which are very close to the usual values reached by the high quality natural zeolitic products. Finally, with the aim of testing possible applications of the commercial NaP1-IQE and pilot plant NaP1-Narcea zeolitic products in water decontamination, efficiency for metal uptake from waste waters from electroplating baths was investigate

Development of Low Temperature, Aqueous Synthesis Method of Lead Sulfide Quantum Dots

Quantum dots have become an active area of research in the past decade due to their unique properties. Quantum confinement effects allow for efficient spectral conversion and size tunable fluorescence and absorption peaks. Near infrared spectral converting lead sulfide quantum dots have potential applications in solar power, biological imaging and communications technology. However at Cal Poly, lead sulfide dots have not been synthesized. The quantum dot synthesis currently adapted at Cal Poly encompasses organometallic precursors at high reaction temperatures, producing cadmium selenium dots. The organometallic approach has been found to produce nanocrystals with high quality photoluminescence, but due to its hazardous reaction parameters an environmentally safe synthesis is desired. The aim of this study was to adapt and develop an aqueous “green” synthesis method for producing lead sulfide quantum dots to Cal Poly. The method used within this study, previously reported Jiao, encompasses a low temperature aqueous synthesis method using low toxicity surfactant precursors SDS, CTAB and EDTA dissolved into deionized water heated to 70 C. A solution of lead acetate was injected into the surfactant solution to produce lead ion EDTA complexes. Thiourea solution was then slowly injected to introduce sulfur allowing lead sulfide to form. The formation of lead sulfide could be seen by the transformation of the solution from buff to dark brown. Samples taken from this solution were naturally cooled, centrifuged and rinsed with alcohol and DI water. Fluorescence and absorbance testing was conducted on produced samples to test for the presence of quantum dots. In addition, commercially purchased lead sulfide quantum dots were fluorescence tested for comparison to our samples