Elastic circuits

Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.Peer ReviewedPostprint (published version

ParaDisEO-Based Design of Parallel and Distributed Evolutionary Algorithms

The original publication is available at www.springerlink.comInternational audienceParaDisEO is a framework dedicated to the design of parallel and distributed metaheuristics including local search methods and evolutionary algorithms. This paper focuses on the latter aspect. We present the three parallel and distributed models implemented in ParaDisEO and show how these can be exploited in a user-friendly, flexible and transparent way. These models can be deployed on distributed memory machines as well as on shared memory multi-processors, taking advantage of the shared memory in the latter case. In addition, we illustrate the instantiation of the models through two applications demonstrating the efficiency and robustness of the framework

Space Station Freedom data management system growth and evolution report

The Information Sciences Division at the NASA Ames Research Center has completed a 6-month study of portions of the Space Station Freedom Data Management System (DMS). This study looked at the present capabilities and future growth potential of the DMS, and the results are documented in this report. Issues have been raised that were discussed with the appropriate Johnson Space Center (JSC) management and Work Package-2 contractor organizations. Areas requiring additional study have been identified and suggestions for long-term upgrades have been proposed. This activity has allowed the Ames personnel to develop a rapport with the JSC civil service and contractor teams that does permit an independent check and balance technique for the DMS

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

The Deep Space Network

Tracking and data acquisition research and technology for the DSN is discussed

FPGA-based EMT simulation

With the massive integration of renewable energy and power electronics, the structure of modern power system becomes increasingly complex. This is a great challenge for the secure and reliable operation of large power systems. It has been recognised that Electromagnetic Transients (EMT) simulations play an important role in analysing large power system operation, control and protection. Hence it is desirable to investigate faster and more efficient simulation methods for large-scale power systems. The existing off-line software packages, such as MATLAB and PSCAD, are time-consuming to simulate EMTs of large scale power systems. There is a growing demand to develop cheaper and faster EMT simulation technologies/techniques. The rapid evolution of computing technologies makes it possible to enhance EMT simulations in real-time domain. With fast calculation speed, configurable resources and programmable structure, Field-Programmable Gate Array (FPGA) is a powerful platform for EMT simulation. Therefore, this thesis aims to propose high-performance FPGA-based EMT simulation models and algorithms with improved accuracy, speed, and efficiency. First, Single-Precision, Double-Precision and Mixed-Precision algorithms are proposed and compared to enhance numerical accuracy for the first time. Existing research publications only consider Single-Precision as default option and ignore possible numerical phase shift in FPGA. As a basis for EMT simulation, a library of fundamental power system components is built up, including linear and nonlinear components. Single-Precision and Double-Precision algorithm are using the same precision for all components. Consider component dynamics, the key of Mixed-Precision is simulating linear and non-linear component using Single-Precision and Double-Precision respectively to eliminate phase shift. Hardware structure is also optimized to make these different precision algorithms achievable on single FPGA board. By comparing with the same referenced models in MATLAB, three algorithms are tested via case studies, including linear components, rotating non-linear components on smaller and larger systems. The adaptability of these algorithms is verified effectively in terms of accuracy, resource utilization, and timing. Second, four initialization methods are developed to minimize accumulated error for FPGA-based EMT simulation for the first time. Most researches from non-initialized time point, which will increase random error. To simulate from initial steady state, fast and reliable initialization are worth to be investigated. For necessary information, key issues for FPGA-based initialization are discussed first, including initialization model type, memory unit and sequence. Both VHDL file (.VHD) and Coefficient (.COE) file allows defining initial data. To maximize flexibility, four initialization methods, including Method 1 (physical interface), Method 2 (signal declaration), Method 3 (signal assignment) and Method 4 (COE) file are proposed and provided with detailed programming codes. For ahead-of-time evaluation, routing and timing performances are compared between these four methods, and Method 4 is the simplest method. The implementation structure and algorithm of Method 4 are developed to allow flexible data transfer between different platforms. For flexible scalability, device-level and system-level case studies are both provided to compare practical performance of Method 1-4. Third, a generic MATLAB-to-FPGA toolbox is developed for users to simplify hardware design. This is motivated by FPGA programming is complex and using FPGA to model EMT is more time-consuming for beginners. Without any EMT functionalities, existing translation toolboxes are focused on direct translation from other language to VHDL/Verilog. Therefore, the development toolbox can accelerate beginners to familiarize FPGA-based EMT. In a user-friendly environment, development framework, design features and requirements are developed for fast processing. For general processing form, data format, structure and partition are developed using intelligent MATLAB built-in functions. To support low-level calculations, translation and resource reutilization for using IP CORES are presented. To integrate and control low-level calculations, high-level main controllers using FSM (Finite State Machine) is setting up sequencers for pipelined and non-pipelined stage. A 39-bus network case study is provided to verify the effectiveness of proposed MATLAB-to-FPGA toolbox. To support high-frequency switching, power electronic devices and control systems are also developed for FPGA-based EMT simulation. Existing research focuses on using multi-FPGA to simulate HVDC-MMC system, this research aims at implementing whole HVDC-MMC system operation and control on single FPGA platform. This can help reduce FPGA area cost and improve resource utilization efficiency. As a supplement to existing power system components, power electronic devices, such as IGBT and MMC (Modular Multi-level Converter), are built up in discrete-time mathematical models. Based on trapezoidal rule, the aggregate model of MMC is derived to use only one equivalent module to represent all modules, regardless of arbitrary modules. Control system, such as PWM control and current control loop, is also modelled and simplified to be more suitable for hardware implementation. Optimized strategies, such as shift memory and interpolation, are also proposed to get lower resource utilization and faster calculation speed in FPGA. With these strategies, PWM control block and HVDC-MMC case studies can both be successfully implemented on single FPGA board with high-performance accuracy and resource utilization

Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip

Due to the tight power budget and reduced time-to-market, Systems-on-Chip (SoC) have emerged as a power-efficient solution that provides the functionality required by target applications in embedded systems. To support a diverse set of applications such as real-time video/audio processing and sensor signal processing, SoCs consist of multiple heterogeneous components, such as software processors, digital signal processors, and application-specific hardware accelerators. These components offer different flexibility, power, and performance values so that SoCs can be designed by mix-and-matching them. With the increased amount of heterogeneous cores, however, the traditional interconnects in an SoC exhibit excessive power dissipation and poor performance scalability. As an alternative, Networks-on-Chip (NoC) have been proposed. NoCs provide modularity at design-time because communications among the cores are isolated from their computations via standard interfaces. NoCs also exploit communication parallelism at run-time because multiple data can be transferred simultaneously. In order to construct an efficient NoC, the communication behaviors of various heterogeneous components in an SoC must be considered with the large amount of NoC design parameters. Therefore, providing an efficient NoC design and optimization framework is critical to reduce the design cycle and address the complexity of future heterogeneous SoCs. This is the thesis of my dissertation. Some existing design automation tools for NoCs support very limited degrees of automation that cannot satisfy the requirements of future heterogeneous SoCs. First, these tools only support a limited number of NoC design parameters. Second, they do not provide an integrated environment for software-hardware co-development. Thus, I propose FINDNOC, an integrated framework for the generation, optimization, and validation of NoCs for future heterogeneous SoCs. The proposed framework supports software-hardware co-development, incremental NoC design-decision model, SystemC-based NoC customization and generation, and fast system protyping with FPGA emulations. Virtual channels (VC) and multiple physical (MP) networks are the two main alternative methods to provide better performance, support quality-of-service, and avoid protocol deadlocks in packet-switched NoC design. To examine the effect of using VCs and MPs with other NoC architectural parameters, I completed a comprehensive comparative analysis that combines an analytical model, synthesis-based designs for both FPGAs and standard-cell libraries, and system-level simulations. Based on the results of this analysis, I developed VENTTI, a design and simulation environment that combines a virtual platform (VP), a NoC synthesis tool, and four NoC models characterized at different abstraction levels. VENTTI facilitates an incremental decision-making process with four NoC abstraction models associated with different NoC parameters. The selected NoC parameters can be validated by running simulations with the corresponding model instantiated in the VP. I augmented this framework to complete FINDNOC by implementing ICON, a NoC generation and customization tool that dynamically combines and customizes synthesizable SystemC components from a predesigned library. Thanks to its flexibility and automatic network interface generation capabilities, ICON can generate a rich variety of NoCs that can be then integrated into any Embedded Scalable Platform (ESP) architectures for fast prototying with FPGA emulations. I designed FINDNOC in a modular way that makes it easy to augmenting it with new capabilities. This, combined with the continuous progress of the ESP design methodology, will provide a seamless SoC integration framework, where the hardware accelerators, software applications, and NoCs can be designed, validated, and integrated simultaneously, in order to reduce the design cycle of future SoC platforms

Trade-off analysis of modes of data handling for earth resources (ERS), volume 2

For abstract, see N75-26470