Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters

Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output stage based on a low dropout regulator stage. For converters such as 12–5V, 5–3.3V and 5–1.5V, the technique provides efficiency improvement factors of 2, 1.33 and 3 respectively, in compared to linear converters with same input-output combinations. In a 5–1.5V SCALDO regulator, using thin profile supercapacitors in the range of fractional farads to few farads, this translates to an approximate end to end efficiency of near 90%. However, there were concerns that this patented technique is merely a variation of well-known switched capacitor (charge pump) converters. This paper is aimed at providing a broad overview of the capability of SCALDO technique with generalized theory, indicating its capabilities and limitations, and comparing the practical performance with a typical switched capacitor converter of similar current capability

STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

A Silicon Carbide Power Management Solution for High Temperature Applications

The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor materials with the potential of breaking through the limitations of traditional silicon. Gallium nitride (GaN) and silicon carbide (SiC), both of which are wide bandgap materials, have garnered the attention of researchers and gradually gained market share. Although these wide bandgap power devices enable more ambitious commercial applications compared to their silicon-based counterparts, reaching their potential is contingent upon developing integrated circuits (ICs) capable of operating in similar environments. The foundation of any electrical system is the ability to efficiently condition and supply power. The work presented in this thesis explores integrated SiC power management solutions in the form of linear regulators and switched capacitor converters. While switched-mode converters provide high efficiency, the requirement of an inductor hinders the development of a compact, integrated solution that can endure harsh operating environments. Although the primary research motivation for wide bandgap ICs has been to provide control and protection circuitry for power devices, the circuitry designed in this work can be incorporated in stand-alone applications as well. Battery or generator powered data acquisition systems targeted towards monitoring industrial machinery is one potential usage scenario

Synthesizable delay line architectures for digitally controlled voltage regulators

Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies

High power-supply rejection current-mode low-dropout linear regulator

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.M.S.Committee Chair: Rincón-Mora, Gabriel; Committee Member: Ghovanloo, Maysam; Committee Member: Leach, W. Marshal

Potential of supercapacitors in novel power converters as semi-ideal lossless voltage droppers

Electrical physics text book theory tells us that charging a capacitor is much less efficient than replenishing the energy in a discharged electro-chemical battery. If a fully discharged capacitor is pumped with a charge of Q coulombs, it stores 1/2QV while dissipating the same amount of energy in the loop resistance. However, if the same charge is pumped into a re-chargeable electrochemical cell of voltage V the energy stored in the cell is QV, while the wasted energy is determined by the loop resistance and the voltage difference across the resistance. If a rechargeable battery pack is to be replaced by a supercapacitor module, this difference could seriously affect the design of power converters required, since the power converter should stop charging at a certain point to avoid overcharging the capacitor bank. However, if a useful resistive load such as heater, DC-DC converter, inverter or a lamp load is used as a part of the loop resistance in a capacitor charging loop, a significant part of this loss can be recovered. One example of this is in the supercapacitor assisted low drop-out regulator (SCALDO) technique. This paper will detail the concept of circumvention of RC loop charging loss, theoretically quantifying the same in a generalized circuit, demonstrating how this can be applied in completely novel circuit topologies such as the supercapacitor assisted LED (SCALED) converter. The paper will provide experimental results of selected SCALDO implementations and early results of SCALED technique to support this theory

Evaluation and implementation of a 5-level hybrid DC-DC converter

In this work, a hybrid voltage regulator topology is analyzed, implemented, and evaluated. The common topologies of DC-DC converters have proven to be lacking in some aspects, such as integrability for buck converters, or maximum efficiency for switched-capacitor regulators. The hybrid topology tackles these shortcomings by combining the advantages of switched-capacitor and inductor-based voltage regulators. A 5-level buck converter is evaluated, implemented, and compared to other converter implementations using the same components. The 5-Level Buck converter can achieve 5 different levels, allowing it to cover 4 operation regions, each between 2 levels. Accordingly, it covers a wide range of output voltages. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it cheaper, smaller in size, and much more efficient. Simulations show proper functionality of the 5-Level topology, while putting restrictions on the inductor size, efficiency, and component footprint (or total converter area). A test PCB is implemented for verification of the functionality and experimental measurements show that for the same switching frequency and inductor size, the 5-level buck converter achieves up to 15% efficiency improvement over a conventional buck converter and a 3-level buck converter at certain output voltage ranges. Peak efficiency of 94% has been achieved by the 5-Level hybrid converter, which includes all external switching and conduction losses. The proposed hybrid topology proved to yield high conversion efficiency even in the face of component size limitations, which indicates potential benefit in using multilevel converters for several off-chip as well as on-chip applications

A novel control mechanism for hybrid 5-level DC-DC converter for higher switching frequency and lower voltage ripple

The introduction and development of hybrid DC-DC converters present a valuable opportunity in on-chip power management, as they combine the advantages of buck and switched-capacitor converters while alleviating shortcomings such as conversion efficiency and sizing requirements. In this paper, a new control methodology is presented for the recently developed 5-level hybrid DC-DC converter, which utilizes the Virtex 5 LX50T FPGA to drive the converter. This control method allows for a higher switching frequency of 1MHz and an improved conversion efficiency while also allowing for dynamic voltage control based on the desired output voltage. Simulations as well as a test circuit are used to illustrate the proper control functionality, with tabulated results that showcase the efficiency advantage over prior control methods as well as the buck and 3-level hybrid converters