Transient Analysis of Warm Electron Injection Programming of Double Gate SONOS Memories by means of Full Band Monte Carlo Simulation

In this paper we investigate "Warm Electron Injection" as a mechanism for NOR programming of double-gate SONOS memories through 2D full band Monte Carlo simulations. Warm electron injection is characterized by an applied VDS smaller than 3.15 V, so that electrons cannot easily accumulate a kinetic energy larger than the height of the Si/SiO2 barrier. We perform a time-dependent simulation of the program operation where the local gate current density is computed with a continuum-based method and is adiabatically separated from the 2D full Monte Carlo simulation used for obtaining the electron distribution in the phase space. In this way we are able to compute the time evolution of the charge stored in the nitride and of the threshold voltages corresponding to forward and reverse bias. We show that warm electron injection is a viable option for NOR programming in order to reduce power supply, preserve reliability and CMOS logic level compatibility. In addition, it provides a well localized charge, offering interesting perspectives for multi-level and dual bit operation, even in devices with negligible short channel effects

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Commercialization of germanium based nanocrystal memory

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.This thesis explores the commercialization of germanium-based nanocrystal memories. Demand for smaller and faster electronics and embedded systems supports the development of high-density, low-power non-volatile electronic memory devices. Flash memory cells designed for ten years of data retention require the use of a thick tunneling oxide. This compromises writing and reading speed as well as endurance. A smaller device size can be achieved and speed and can be improved by decreasing the oxide thickness. However, significant charge leakage will occur if the oxide is too thin, which will reduce the data retention time dramatically. This imposes a limit to the amount by which the oxide thickness can be decreased in conventional devices. Research has shown that by incorporating nanocrystals in the tunnel oxide, charge traps are created which reduce charge leakage and improve endurance through charge-storage redundancy. By replacing the conventional floating gate memory with one using Si or Ge nanocrystals, the nonvolatile memory exhibits high programming speed with low programming voltage and superior retention time, and yet is compatible with conventional silicon technology. This thesis provides an analysis of competing technologies, an intellectual property analysis, costs modeling as well as ways to improve nanocrystal memories in order to compete with other forms of emerging technologies to replace conventional Flash memories.by Kian Chiew Seow.M.Eng

Top-down Si nanowire technology in discrete charge storage nonvolatile memory application

Ph.DDOCTOR OF PHILOSOPH

Study on application of high-K dielectric materials for discrete charge storage memory

Ph.DDOCTOR OF PHILOSOPH

Doped Metal Oxide High-K Gate Dielectric for Nonvolatile Memory and Light Emitting Applications

The zirconium-doped hafnium oxide (ZrHfO) high-k thin film has excellent gate dielectric properties, such as a higher crystallization temperature, a lower defect density, and a larger effective k value. As a promising high-k material, ZrHfO has been utilized for both nonvolatile memory (NVM) and light emitting applications. Replacing the polycrystalline Si floating gate, the discrete nanocrystals embedded ZrHfO gate dielectric can achieve promising NVM performance. On the other hand, warm white light can be emitted from the thermal excitation of nano-resistors form from the dielectric breakdown of the ZrHfO Metal-Oxide-Semiconductor (MOS) capacitor. This novel solid state incandescent light emitting device (SSI-LED) unveils a new concept for the lighting device evolution. Nanocrystalline cadmium sulfide (nc-CdS) embedded ZrHfO high-k NVMs have been fabricated to reduce the frequency dispersion problem caused by defects at the nanocrystal/dielectric interface. The nc-CdS embedded device can retain about 53% of originally trapped holes for 10 years and exhibit outstanding memory function at low operation voltage. The study on the nc-CdSe embedded ZrHfO NVMs shows that the high temperature enhances the hole trapping but decreases the electron trapping. Based on the different temperature dependences, the stored electrons release faster than stored holes. The raised temperature accelerates the dielectric breakdown process by increasing defect densities and defect effective conduction radii. The post deposition annealing (PDA) atmosphere is critical to the electrical and light emission characteristics of ZrHfO SSI-LEDs. It affects the dielectric breakdown, light emission intensity and efficiency by changing compositions of the high-k stack and the nano-resistor. The electrical properties, i.e., effective resistances and Schottky barrier heights of nano-resistors have been estimated. The nano-resistor behaves neither like a conductor nor like a semiconductor. Moreover, the barrier height inhomogeneity is observed due to the random and complicated nano-resistor formation. The embedding method and the heavily doped p-Si substrate have been employed to enhance the light emission from ZrHfO SSI-LEDs. Lastly, extensive applications of this novel nano-resistor device for on-chip optical interconnects and as diode-like anti-fuses have been discussed

Doped Metal Oxide High-K Gate Dielectric for Nonvolatile Memory and Light Emitting Applications

The zirconium-doped hafnium oxide (ZrHfO) high-k thin film has excellent gate dielectric properties, such as a higher crystallization temperature, a lower defect density, and a larger effective k value. As a promising high-k material, ZrHfO has been utilized for both nonvolatile memory (NVM) and light emitting applications. Replacing the polycrystalline Si floating gate, the discrete nanocrystals embedded ZrHfO gate dielectric can achieve promising NVM performance. On the other hand, warm white light can be emitted from the thermal excitation of nano-resistors form from the dielectric breakdown of the ZrHfO Metal-Oxide-Semiconductor (MOS) capacitor. This novel solid state incandescent light emitting device (SSI-LED) unveils a new concept for the lighting device evolution. Nanocrystalline cadmium sulfide (nc-CdS) embedded ZrHfO high-k NVMs have been fabricated to reduce the frequency dispersion problem caused by defects at the nanocrystal/dielectric interface. The nc-CdS embedded device can retain about 53% of originally trapped holes for 10 years and exhibit outstanding memory function at low operation voltage. The study on the nc-CdSe embedded ZrHfO NVMs shows that the high temperature enhances the hole trapping but decreases the electron trapping. Based on the different temperature dependences, the stored electrons release faster than stored holes. The raised temperature accelerates the dielectric breakdown process by increasing defect densities and defect effective conduction radii. The post deposition annealing (PDA) atmosphere is critical to the electrical and light emission characteristics of ZrHfO SSI-LEDs. It affects the dielectric breakdown, light emission intensity and efficiency by changing compositions of the high-k stack and the nano-resistor. The electrical properties, i.e., effective resistances and Schottky barrier heights of nano-resistors have been estimated. The nano-resistor behaves neither like a conductor nor like a semiconductor. Moreover, the barrier height inhomogeneity is observed due to the random and complicated nano-resistor formation. The embedding method and the heavily doped p-Si substrate have been employed to enhance the light emission from ZrHfO SSI-LEDs. Lastly, extensive applications of this novel nano-resistor device for on-chip optical interconnects and as diode-like anti-fuses have been discussed

NANOSTRUCTURED MATERIALS FOR MEMORY APPLICATIONS

Ph.DDOCTOR OF PHILOSOPH