Oscillator phase noise: a tutorial

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1/f noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM-PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exhibits good performance, and suggest new oscillator topologies. Tuned LC and ring oscillator circuit examples are presented to reinforce the theoretical considerations developed. Simulation issues and the accommodation of amplitude noise are considered in appendixes

A general theory of phase noise in electrical oscillators

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed

A study of phase noise and jitter in submicron CMOS phase-locked loop circuits

Phase-locked loops (PLLs) are widely used in communication systems. With the continuously expanding of market for high speed, portable communication devices, low noise CMOS submicron integrated circuit designs of PLL for different applications are in large demand. In this dissertation, phase noise and jitter properties of PLL and its building blocks are investigated both at the physical and system levels. At the physical level, hot carrier effect in submicron MOSFETs has been considered. As one of the most dominant noise sources of PLL, the voltage-controlled oscillator (VCO) is considered when investigating the noise degradation induced by the hot carrier effect. Experimental results of jitter degradation due to hot carrier effects are presented for different ring oscillator types VCOs designed in 0.5 micron n-well CMOS technology. An increase in RMS jitter by 25% and 10% decrease in oscillation frequency of VCO can be observed after 4 hours hot carrier stress. The hot carrier induced noise degradation on PLL is also presented based on the performance degradation in VCO. Simulation results show 40% decrease in VCO gain after 4 hours stress and a 23% decrease in damping factor and loop bandwidth. Moreover, degradation on PLL noise performance includes a left shift peak in phase noise and a 17% increase in RMS jitter. At the system level, noise sources in a PLL system are investigated including the input reference noise, VCO noise and the frequency divider noise. Phase noise prediction method for PLL is developed. Experimental phase noise measurement results on 0.5 micron CMOS PLL systems based on different types of VCOs are in close agreement with the predicted phase noise. Therefore, the phase noise prediction method is verified. On the other hand, a 3 GHz adaptive bandwidth PLL based on LC-VCO is designed in 0.25 micron n-well CMOS technology to investigate the phase noise and jitter performance by varying the loop parameters. By considering the noise simulation results based on the adaptive bandwidth feature and the quality factor of the on-chip inductor, PLL loop parameters can be carefully chosen at the design phase to achieve an optimal noise performance

Phase Noise in CMOS Phase-Locked Loop Circuits

Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

High Speed CMOS VCO For Advanced Communications [TK7871.99.M99 C435 2003 f rb][Microfiche 7271].

Peningkatan keperluan bagi komunikasi tanpa wayar dalam suara dan data telah memotivasikan kerja-kerja untuk meningkatkan tahap intregrasi dalam pemancar-penerima berfrekuensi radio (RF) baru-baru ini. The fast growing demand of wireless communications for voice and data has driven recent efforts to dramatically increase the level of integration in RF transceivers

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort