Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Design of event-driven automatic gain control and high-speed data path for multichannel optical receiver arrays

The internet has become the ubiquitous tool that has transformed the lives of all of us. New broadband applications in the field of entertainment, commerce, industry, healthcare and social interactions demand increasingly higher data rates and quality of the networks and ICT infrastructure. In addition, high definition video streaming and cloud services will continue to push the demand for bandwidth. These applications are reshaping the internet into a content-centric network. The challenge is to transform the telecom optical networks and data centers such that they can be scaled efficiently, at low cost. Furthermore, from both an environmental and economic perspective, this scaling should go hand in hand with reduced power consumption. This stems from the desire to reduce CO2 emission and to reduce network operating costs while offering the same service level as today. In the current architecture of the internet, end-users connect to the public network using the access network of an internet service provider (ISP). Today, this access network either reuses the legacy copper or coaxial network or uses passive optical network (PON) technologies, among which the PON is the most energy efficient and provides the highest data rates. Traffic from the access network is aggregated with Ethernet switches and routed to the core network through the provider edge routers, with broadband network gateways (BNGs) to regulate access and usage. These regional links are collectively called the metro network. Data centers connect to the core network using their own dedicated gateway router. The problem of increasing data rates, while reducing the economic and environmental impact, has attracted considerable attention. The research described in this work has been performed in the context of two projects part of the European Union Seventh Framework Programme (FP7), which both aim for higher data rates and tight integration while keeping power consumption low. Mirage targets data center applications while C3PO focuses on medium-reach networks, such as the metro network. Specifically, this research considers two aspects of the high-speed optical receivers used in the communication networks: increasing dynamic range of a linear receiver for multilevel modulation through automatic gain control (AGC) and integration of multiple channels on a single chip with a small area footprint. The data centers of today are high-density computing facilities that provide storage, processing and software as a service to the end-user. They are comprised of gateway routers, a local area network, servers and storage. All of this is organized in racks. The largest units contain over 100 000 servers. The major challenges regarding data centers are scalability and keeping up with increasing amounts of traffic while reducing power consumption (of the devices as well as the associated cooling) and keeping cost minimal. Presently, racks are primarily interconnected with active optical cables (AOCs) which employ signal rates up to 25 Gb/s per lane with non-return-to-zero (NRZ) modulation. A number of technological developments can be employed in AOCs of the future to provide terabit-capacity optical interconnects over longer distances. One such innovation is the use of multilevel modulation formats, which are more bandwidth-efficient than traditional NRZ modulation. Multilevel modulation requires a linear amplifier as front-end of the optical receiver. The greater part of this dissertation discusses the design and implementation of an AGC system for the data path of a linear transimpedance amplifier (TIA). The metro network is the intermediate regional network between the access and core network of the internet architecture, with link lengths up to 500 km. It is estimated that in the near future metro-traffic will increase massively. This growth is attributed mainly to increasing traffic from content delivery networks (CDNs) and data centers, which bypass the core network and directly connect to the metro network. Internet video growth is the major reason for traffic increase. This evolution demands increasingly higher data rates. Today, dense wavelength division multiplexing (DWDM) is widely recognized as being necessary to provide data capacity scalability for future optical networks, as it allows for much higher combined data rates over a single fiber. At the receiver, each wavelength of the demultiplexed incoming light is coupled to a photo diode in a photo diode array which is connected to a dedicated lane of a multichannel receiver. The high number of channels requires small physical channel spacing and tight integration of the diode array with the receiver. In addition, active cooling should be avoided, such that power consumption per receiver lane must be kept low in order not to exceed thermal operation limits. The second component of this work presents the development of an integrated four-channel receiver, targeting 4 × 25 Gb/s data rate, with low power consumption and small footprint to support tight integration with a p-i-n photo diode array with a 250 μm channel pitch. Chapter 1 discusses the impact of increasing data rates and the desire to reduce power consumption on the design of the optical receiver component, in wide metropolitan area networks as well as in short-reach point-to-point links in data centers. In addition, some aspects of integrated analog circuit design are highlighted: the design flow, transistor hand models, a software design tool. Also, an overview of the process technology is given. Chapter 2 provides essential optical receiver concepts, which are required to understand the remainder of the work. Fundamentals of feedback AGC systems are discussed in the first part of Chapter 3. A basic system model is presented in the continuous-time domain, in which the variable gain amplifier (VGA) constitutes the multistage datapath of a linear optical receiver. To enable reliable reception of multilevel modulation formats, the VGA requires controlled frequency response and in particular limited time-domain overshoot across the gain range. It is argued that this control is hard to achieve with fully analog building blocks. Therefore, an event-driven approach is proposed as an extension of the continuous-time system. Both the structural and behavioral aspects are discussed. The result is a system model of a quantized AGC loop, upon which the system-level design, presented in Chapter 4, is based. In turn, Chapter 5 discusses the detailed implementation of the various building blocks on the circuit level and presents experimental results that confirm the feasibility of the proposed approach. Chapter 6 discusses the design and implementation of a 4 × 25 Gb/s optical receiver array for NRZ modulation with a small area footprint. The focus lies on the input stages and techniques to extend bandwidth and dynamic range are presented. Measurement results for NRZ and optical duobinary (ODB) modulation are presented, as well as the influence of crosstalk on the performance. Finally, Chapter 7 provides an overview of the foremost conclusions of the presented research and includes suggestions for future research. Two appendices are included. Appendix A gives an overview of the general network theorem (GNT), which is used throughout this work and which has been implemented numerically. The results from Appendix B, the analysis of a two-stage opamp compensated with capacitance multipliers, were used to design a building block for the AGC system

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Moving Towards Analog Functional Safety

Over the past century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power systems. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The standard ISO 26262 related to functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardizing fault modeling, injection and simulation mainly focused on digital circuits and disregarding analog ones. An initial attempt is being made with the IEEE P2427 standard draft standard that started to give this field a structured and formal organization. In this context, new fault models, injection, and abstraction methodologies for analog circuits are proposed in this thesis to enhance this application field. The faults proposed by the IEEE P2427 standard draft standard are initially evaluated to understand the associated fault behaviors during the simulation. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. These new defects proposed are required because digital stuck-at-fault models where a transistor is frozen in on-state or offstate may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. Then, for validating the proposed defects models, a novel predictive fault grouping based on faulty AC matrices is applied to group faults with equivalent behaviors. The proposed fault grouping method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself to faulty AC simulations. Using AC simulations results in two different methods that allow grouping faults with the same frequency response are presented. The first method is an AC-based grouping method that exploits the potentialities of the S-parameters ports. While the second is a Circle-based grouping based on the circle-fitting method applied to the extracted AC matrices. Finally, an open-source framework is presented for the fault injection and manipulation perspective. This framework relies on the shared semantics for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. As a use case for the proposed framework, a process of analog fault injection is discussed. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. The framework is entirely written in C++, and its APIs are also interfaced with Python. The entire framework is open-source and available on GitHub. The last part of the thesis presents abstraction methodologies that can abstract transistor level models into Verilog-AMS models and Verilog- AMS piecewise and nonlinear models into C++. These abstracted models can be integrated into heterogeneous systems. The purpose of integration is the simulation of heterogeneous components embedded in a Virtual Platforms (VP) needs to be fast and accurate

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions