Direct synthesis of timed asynchronous circuits

Journal ArticleThis paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. Our synthesis procedure begins with a deterministic signal transition graph specification to which timing constraints can be added. First, a timing analysis extracts the timed concurrency relation and timed causality relation between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding a shortest path in the graph. Our method does not have the state explosion problem while the synthesized circuits have nearly the same area with the previous timed circuits

Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines

Journal ArticleAbstract This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient single-cube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor - more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before

Synthesis of asynchronous controllers using integer linear programming

A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. Techniques that are capable of checking implementability conditions, such as complete state coding, and deriving a gate netlist to implement the specified behavior are presented. These techniques can handle Petri net specifications consisting of several thousands of transitions and provide a significant speed-up compared with techniques that have previously been proposed.Peer ReviewedPostprint (published version

Síntese de Circuitos Assíncronos com Conflitos: uma Abordagem baseada em Regiões

Doutoramento em Engenharia Electrónica e TelecomunicaçõesCircuitos assíncronos são uma área de investigação presentemente com um largo número de pessoas envolvidas, quer na indústria quer nos meios académicos. Após um longo período de actividade marginal, tópicos como especificação, análise, síntese ou verificação merecem a atenção da comunidade científica. Uma média anual de publicações superior a 100 durante a última década é disso mesmo uma prova. A taxionomia habitual de circuitos assíncronos tem por base o modelo de atraso sob o qual se assume aqueles funcionarem correctamente. A classe dos circuitos assíncronos independentes da velocidade (speed independent asynchronous circuits), que estão na base do trabalho apresentado nesta tese, assumem um atraso das portas lógicas finito mas sem limite superior conhecido e um atraso dos fios de interconexão nulo ou pelo menos desprezável face ao atraso das portas. A especificação nesta classe é normalmente feita usando dois tipos de grafos: grafos de estados, um formalismo tendo por base os estados do circuito, e grafos de transições de sinais, uma classe de redes de Petri onde se descreve as relações de causalidade e concorrência entre os eventos _ transições de sinais _ no circuito. Existem disponíveis ferramentas de síntese automática de circuitos assíncronos independentes da velocidade, merecendo Petrify a nossa especial referência. Dois cenários não são contemplados por estas ferramentas, uma vez que infringem uma condição necessária para a existência de uma solução puramente digital independente da velocidade. Um é caracterizado pela existência de não-persistências envolvendo sinais internos ou de saída, situação típica em árbitros e sincronizadores. Uma metodologia de projecto é apresentada que permite a geração de uma solução recorrendo ao uso de ferramentas de síntese para circuitos independentes da velocidade. Um procedimento de transformação toma, à entrada, uma especificação contendo não-persistências e fornece, à saída, um conjunto de componentes especiais, que lidam com as não-persistências, e uma especificação apropriada para alimentar a ferramenta de síntese. Estabelece-se uma relação entre estados não persistentes e regiões concorrentes, que actuam como secções críticas do sistema. Controlando o acesso a essas regiões, por via da introdução de componentes especiais em hardware, parcialmente analógicos, desempenhando o papel de árbitros, transferem-se os conflitos para os árbitros, ficando o resto do circuito deles isento. Na metodologia proposta, toda a transformação toma a forma de um simples produto de sistemas de transições. Isto resulta da possibilidade de representar os vários passos do procedimento de inserção dos árbitros através de factores multiplicativos. O produto de sistemas de transições goza, se visto em termos de isomorfismo e de grafo alcançável a partir do estado inicial, das propriedades comutativa e associativa, pelo que a ordem de processamento é irrelevante para o resultado final O outro cenário corresponde à existência de não-comutatividades entre eventos de entrada. O problema é analisado e diferentes abordagens para o ultrapassar são apresentadas. Uma das abordagens aponta no sentido da transformação das não-comutatividades em não-persistências, aplicando-se de seguida a metodologia desenvolvida para estas. Uma outra abordagem sugere o controlo das não-comutatividades por via da inserção de dispositivos específicos de arbitragem. A análise apresentada deve ser aprofundada por forma a se definir a metodologia mais apropriada para a resolução deste tipo de conflitos..Asynchronous circuits are a subject of research currently with a large number of people involved, both from academy and industry. After a long period of time of marginal activity, topics like speci_cation, analysis, synthesis, veri_cation have deserve attention of the research community. An average of more then 100 papers per year in the last decade in an evidence of that. The common taxonomy of asynchronous circuits is based on the delay model under which they are assumed to properly operate. The class of speed independent asynchronous circuits, which assumes an unbounded gate delay model, that is, gates have a _nite, no upper limited delay while wires interconnecting gates are assumed to have negligible delays, underlies the work presented in this thesis. Speci_cations are usually described using two types of graph models: state graphs, a state-based formalism, and signal transition graphs, a class of Petri nets. Automatic synthesis tools exist, with Petrify deserving our special attention. Two scenarios in speci_cation are not accepted by these tools, because they infringe a speed independent necessary condition. One is characterized by non-persistences involving non-input signals, which are typical in arbiters and synchronizers. A design methodology is presented that allows the use of existing speed independent tools to derive an implementation for such speci_cations. A transformation procedure takes a speci_cation with non-persistences at input and delivers both a net list of special components managing the non-persistences and a speci_cation suitable to feed the logic synthesis tool. Non-persistences are modeled as exclusion relations among regions, which act like critical sections of the system. Introducing special, partial analog components, acting as arbiters, access to these regions are controlled, transferring the con_ict points to the arbiters and leaving the remainder of the speci_cation free from con_icts. In the proposed methodology the overall transformation takes the simple form of products of transition systems. In the region-based model used, the several steps for the insertion of an arbiter into the speci_cation can be represented as transition system factors. Thus the product form can be achieved. Up to reachability and isomorphism, the product of transition systems holds the commutative and associative properties. The order of processing of di_erent non-persistences is thus irrelevant to the _nal result. The other scenario corresponds to the existence of non-commutativities between input events. The problem is analyzed and di_erent approaches to solve it are discussed. One approach suggests the transformation of the non-commutativities into nonpersistences, allowing for the subsequent application of the methodology developed for non-persistences. Another approach suggests the control of non-commutativities by means of the insertion of speci_c arbitration entities. Non-commutativities must however be further analyzed in order to de_ne and develop a proper methodology to solve this kind of con_icts

Structural Methods for the Synthesis of Speed-Independent Circuits

Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally expensive methods. This work presents new methods for the synthesis of speed-independent circuits from a new perspective, overcoming both the analysis and computation complexity bottlenecks. The circuits are specified by free-choice signal transition graphs (STG's), a subclass of interpreted Petri nets. The synthesis approach is divided into the following steps: correctness, binary coding, implementability conditions, and logic synthesis. Each step is efficiently implemented by applying a set of structural techniques that analyze STG's without explicitly enumerating the underlying state space. Experimental results show that circuits can be generated from specifications that exceed in several orders of magnitude the largest STG's ever synthesized---with over 1..

Structural methods for the synthesis of speed-independent circuits

Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be applied to any STG that can be covered by State Machines and, in particular to all live and safe free-choice STGs. Significant improvements with regard to existing structural methods are provided. The new techniques have been implemented in an experimental tool that has been able to synthesize specifications with over 10/sup 27/ markings, some of them being non-free choice.Peer Reviewe

Structural Methods for the Synthesis of Speed-Independent Circuits

The synthesis of asynchronous circuits is inherently complex for two different aspects. Firstly, the required cumbersome theoretical analysis introduces restrictive correctness conditions that complicate the synthesis process. Secondly, even for small asynchronous systems, its inherent concurrency implies the analysis of a huge number of states. This vast space of states requires computation intensive methods that often cannot be successfully completed. This work tackles the synthesis of asynchronous circuits from a new perspective, overcoming both the analysis and computation complexity bottlenecks. The tackled problem starts from behavioral descriptions of asynchronous circuits based on a Petri net modeling formalism. The asynchronous circuits to be generated are described by means of a class of interpreted Petri nets named Signal Transition Graphs (STGs). Based on a subset of this mathematical formalization (the free-choice STGs), the steps that should be followed in the synthesis p..