Coherent beam combining with multilevel optical phase-locked loops

Coherent beam combining (CBC) technology holds the promise of enabling laser systems with very high power and near-ideal beam quality. We propose and demonstrate a novel servo system composed of multilevel optical phase lock loops. This servo system is based on entirely electronic components and consequently can be considerably more compact and less expensive compared to servo systems made of optical phase/frequency shifters. We have also characterized the noise of a 1064 nm Yb-doped fiber amplifier to determine its effect on the CBC and studied theoretically the efficiency of combining a large array of beams with the filled-aperture implementation. In a proof-of-concept experiment we have combined two 100 mW 1064 nm semiconductor lasers with an efficiency of 94%

Coded spread spectrum digital transmission system design study

Results are presented of a comprehensive study of the performance of Viterbi-decoded convolutional codes in the presence of nonideal carrier tracking and bit synchronization. A constraint length 7, rate 1/3 convolutional code and parameters suitable for the space shuttle coded communications links are used. Mathematical models are developed and theoretical and simulation results are obtained to determine the tracking and acquisition performance of the system. Pseudorandom sequence spread spectrum techniques are also considered to minimize potential degradation caused by multipath

DSN advanced receiver: Breadboard description and test results

A breadboard Advanced Receiver for use in the Deep Space Network was designed, built, and tested in the laboratory. Field testing was also performed during Voyager Uranus encounter at DSS-13. The development of the breadboard is intended to lead towards implementation of the new receiver throughout the network. The receiver is described on a functional level and then in terms of more specific hardware and software architecture. The results of performance tests in the laboratory and in the field are given. Finally, there is a discussion of suggested improvements for the next phase of development

Variable domain transformation for linear PAC analysis of mixed-signal systems

This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commercial RF simulators, the circuit’s linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage-domain models, instead of being modeled as strongly-nonlinear systems directly

Theory of phaselock techniques as applied to aerospace transponders

Phaselock techniques as applied to aerospace transponder

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Phase locked loop synchronization for direct detection optical PPM communication systems

Receiver timing synchronization of an optical pulse position modulation (PPM) communication system can be achieved using a phase locked loop (PLL) if the photodetector output is properly processed. The synchronization performance is shown to improve with increasing signal power and decreasing loop bandwidth. Bit error rate (BER) of the PLL synchronized PPM system is analyzed and compared to that for the perfectly synchronized system. It is shown that the increase in signal power needed to compensate for the imperfect synchronization is small (less than 0.1 dB) for loop bandwidths less than 0.1% of the slot frequency

Analysis of a first order phase locked loop in the presence of Gaussian noise

A first-order digital phase locked loop is analyzed by application of a Markov chain model. Steady state loop error probabilities, phase standard deviation, and mean loop transient times are determined for various input signal to noise ratios. Results for direct loop simulation are presented for comparison

Design and layout strategies for integrated frequency synthesizers with high spectral purity

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequen

Application of optical phase lock loops in coherent beam combining

Coherent Beam Combining (CBC) technology holds the promise of enabling laser systems with very high power and near-ideal beam quality. In this work we propose and demonstrate a novel CBC servo system using optical phase lock loops for phase control. This servo system is based on entirely electronic components and, consequently, can be considerably more compact and less expensive compared to servo systems made of optical phase/frequency shifters. In the proof-of-concept experiments we have combined two 100mW 1064nm commercial semiconductor lasers with the filled-aperture approach at an efficiency of 94% and also two 50mW 1538nm commercial semiconductor lasers using the tiled-aperture approach with a strehl ratio of 0.9. In addition, we also present a theoretical consideration of the influence of various sources of noise on the combining efficiency of a cascaded filled-aperture CBC system