Stochastic process design kits for photonic circuits based on polynomial chaos augmented macro-modelling

Fabrication tolerances can significantly degrade the performance of fabricated photonic circuits and process yield. It is essential to include these stochastic uncertainties in the design phase in order to predict the statistical behaviour of a device before the final fabrication. This paper presents a method to build a novel class of stochastic-based building blocks for the preparation of Process Design Kits for the analysis and design of photonic circuits. The proposed design kits directly store the information on the stochastic behaviour of each building block in the form of a generalized-polynomial-chaos-based augmented macro-model obtained by properly exploiting stochastic collocation and Galerkin methods. Using these macro-models, only a single deterministic simulation is required to compute the stochastic moments of any arbitrary photonic circuit, without the need of running a large number of time-consuming circuit simulations thereby dramatically improving simulation efficiency. The effectiveness of the proposed approach is verified by means of classical photonic circuit examples with multiple uncertain variables

Optimization techniques for high-performance digital circuits

The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on circuit opti-mization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The de-sign metrics are not just delay, transition times, power and area, but also signal integrity and manufacturability. This tutorial paper discusses some of the recently pro-posed methods of circuit optimization, with an emphasis on practical application and methodology impact. Circuit optimization techniques fall into three broad categories. The rst is dynamic tuning, based on time-domain simulation of the underlying circuit, typically combined with adjoint sensitivity computation. These methods are accurate but require the specication of in-put signals, and are best applied to small data- ow cir-cuits and \cross-sections " of larger circuits. Ecient sensitivity computation renders feasible the tuning of cir-cuits with a few thousand transistors. Second, static tuners employ static timing analysis to evaluate the per-formance of the circuit. All paths through the logic are simultaneously tuned, and no input vectors are required. Large control macros are best tuned by these methods. However, in the context of deep submicron custom de-sign, the inaccuracy of the delay models employed by these methods often limits their utility. Aggressive dy-namic or static tuning can push a circuit into a precip-itous corner of the manufacturing process space, which is a problem addressed by the third class of circuit op-timization tools, statistical tuners. Statistical techniques are used to enhance manufacturability or maximize yield. In addition to surveying the above techniques, topics such as the use of state-of-the-art nonlinear optimization methods and special considerations for interconnect siz-ing, clock tree optimization and noise-aware tuning will be brie y considered.

Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing

As CMOS scales down to sub-50 nm, it faces critical dimensions of charge and matter granularities, leading to the drastic increase of device parameter dispersion, named statistical variability, which is one of the main contemporary challenges for further downscaling and makes each device atomistically different leading to broad dispersion of their electrical characteristics. In addition, device reliability concerns gain inertia; among them Bias Temperature Instability (BTI) shortens device lifetime by trapping charges in defect states of the insulator or at the interface. The interplay between statistical variability and BTI results in more variations on device performance and thus greatly affect circuit performance. In turn design methodologies must evolve towards variability and reliability aware design. To do so statistical compact models including both the effects of statistical variability and BTI-induced ageing are required for the large-scale statistical circuit simulation of variability and reliability. In this study, the application of accurate compact models, that describe performance variation in the presence of both statistical variability and reliability at arbitrary BTI-induced ageing levels, to SRAM circuit simulation is described. Both SRAM cell stability and write performance are evaluated and it is seen that, due to the accurate description of device performance distributions provided by the compact models and the sensitivity of these SRAM performance metrics on device performance, the approach presented here is better suited to high-sigma statistical circuit analysis than conventional approaches based upon assumed Gaussian distributions. The approach is demonstrated using a 25 nm gate length bulk MOSFET whose performance variation is obtained from statistical TCAD simulation using the GSS simulator GARAND. The simulated performance data is then used directly as the target for BSIM4 compact model extraction that ensures device figures of merit are well resolved for each device in a statistical ensemble. The distribution of compact model parameters is then generalised into an algebraic form using Generalized Lambda Distribution (GLD) methods, so that a sufficiently large number of compact models can later be generated and interpolated at arbitrary ageing levels. Finally compact models generated in this way are used to evaluate SRAM write performance and stability under the influence of statistical variability and BTI-induced ageing

Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method

Tool for fast mismatch analysis of analog circuits

A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated via the analysis of a Miller OTA in two different configurations and a linearized CMOS transconductor. The CPU time is reduced by a factor of 25 to 90 with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations