Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Secure HfO2 based charge trap EEPROM with lifetime and data retention time modeling

Trusted computing is currently the most promising security strategy for cyber physical systems. Trusted computing platform relies on securely stored encryption keys in the on-board memory. However, research and actual cases have shown the vulnerability of the on-board memory to physical cryptographic attacks. This work proposed an embedded secure EEPROM architecture employing charge trap transistor to improve the security of storage means in the trusted computing platform. The charge trap transistor is CMOS compatible with high dielectric constant material as gate oxide which can trap carriers. The process compatibility allows the secure information containing memory to be embedded with the CPU. This eliminates the eavesdropping and optical observation. This effort presents the secure EEPROM cell, its high voltage programming control structure and an interface architecture for command and data communication between the EEPROM and CPU. The interface architecture is an ASIC based design that exclusively for the secure EEPROM. The on-board programming capability enables adjustment of programming voltages and accommodates EEPROM threshold variation due to PVT to optimize lifetime. In addition to the functional circuitry, this work presents the first model of lifetime and data retention time tradeoff for this new type of EEPROM. This model builds the bridge between desired data retention time and lifetime while producing the corresponding programming time and voltage

Local Characterization of Resistance Switching Phenomena in Transition Metal Oxides

The development of neuromorphic computing systems that emulate the analog charge states and plasticity of the brain’s neuron-synapse architecture has been a major driver of resistance switching materials exploration. Materials that demonstrate changes in conductance with tunable ratios and volatility of resistance states within a single layer are highly desirable. Although excellent resistance switching device performance has been demonstrated in a range of transition metal oxides, a lack of understanding of the fundamental microscale evolution of a material during resistance switching presents a key limitation to controlling switching parameters. Here, we examine the role of materials defects on local resistance switching structures in two representative transition metal oxide materials: HfOv2 thin films and hydrothermally synthesized VOv2 single crystals. In each material, we seek to clarify the structure of resistance switching domains and the kinetics of domain formation resulting from intentional defect introduction. This thesis is therefore divided into two main parts concerning (1) the introduction of planar defects in HfOv2 filamentary resistance switching devices, and (2) the impact of introduction of point defects on the metal-insulator transition in VOv2 single crystals. Part I (Sections 2 – 3) details investigation of Cu ion migration rates in Cu/HfOv2/p+Si and Cu/HfOv2/TiN devices in which oxide microstructure varies between amorphous, polycrystalline, and oriented polycrystalline. Ion migration across the oxide layer is shown to be rate limiting and faster in polycrystalline layers than in amorphous HfO2 layers at equivalent electric field. Moreover, the 3D shape of conductive filaments is investigated by a scribing atomic force microscopy experiment in Cu/HfOv2/p+Si devices and reveals a broad range of filament shapes under identical electrical stress conditions. Thermal dissipation is interpreted as the principal determinant of filament area, while oxide microstructure is shown to direct the location of filaments within the device. In part II (Sections 4 – 5), the hysteresis of the metal-insulator transition (switching volatility) in VOv2 is shown to intrinsically derive from nucleation limited transformations in individual particles. Here, hysteresis is a strong function of particle size, but may be increased or decreased by synthesis techniques that affect the concentration and potency of intrinsic point defects. Upon chemical doping with boron at interstitial lattice sites, a unique kinetic effect on the hysteresis of the current driven metal-insulator transition in two terminal BxVOv2 devices is observed. Dependence of the critical switching current on thermal relaxation time and temperature is characterized and recommendations for further kinetic testing are made. Finally, a few experimental extensions of the work presented in this thesis are made in Section 6

Probing technique for energy distribution of positive charges in gate dielectrics and its application to lifetime prediction

The continuous reduction of the dimensions of CMOS devices has increased the negative bias temperature instability (NBTI) of pMOSFETs to such a level that it is limiting their lifetime. This increase of NBTI is caused mainly by three factors: an increase of nitrogen concentration in gate dielectric, a higher operation electrical field, and a higher temperature. Despite of many years’ research work, there are questions on the correctness of the NBTI lifetime predicted through voltage acceleration and extrapolation. The conventional lifetime prediction technique measures the degradation slowly and it typically takes 10 ms or longer to record one threshold voltage shift. It has been reported that NBTI can recover substantially in this time and the degradation is underestimated. To minimize the recovery, ultra-fast technique has been developed and the measurement time has been reduced to the order of microseconds. Once the recovery is suppressed, however, the degradation no longer follows a power law and there is no industry-wide accepted method for lifetime prediction. The objective of this project is to overcome this challenge and to develop a reliable NBTI lifetime prediction technique after freezing the recovery. To achieve this objective, it is essential to have an in-depth knowledge on the defects responsible for the recovery. It has been generally accepted that the NBTI recovery is dominated by the discharge of trapped holes. For the thin dielectric (e.g. < 3 nm) used by current industry, all hole traps are within direct tunnelling distance from the substrate and their discharging is mainly controlled by their energy levels against the Fermi level at the substrate interface. As a result, it is crucial to have the energy distribution of positive charges (PC) in the gate dielectric, but there is no technique available for probing this energy profile. A major achievement of this project is to develop a new technique that can probe the energy distribution of PCs both within and beyond the silicon energy gap. After charging up the hole traps, they are allowed to discharge progressively by changing the gate bias, Vg, in the positive direction in steps. This allows the Fermi level at the interface to be swept from a level below the valence band edge to a level above the conduction band edge, giving the required energy profile. Results show that PCs can vary by one order of magnitude with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps which are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence band edge are from the created defects. The PCs within bandgap saturate for either longer stress time or higher stress temperature. In contrast, the PCs above conduction band edge, namely the anti-neutralization positive charges, do not saturate and their generation is clearly thermally accelerated. This energy profile technique is applicable to both SiON and high-k/SiON stack. It is found that both of them have a high level of as-grown hole traps below the valence band edge and their main difference is that there is a clear peak in the energy density near to the conduction band edge for the High-k/SiON stack, but not for the SiON. Based on this newly developed energy profile technique and the improved understanding, a new lifetime prediction technique has been proposed. The principle used is that a defect must be chargeable at an operation voltage, if it is to be included in the lifetime prediction. At the stress voltage, some as-grown hole traps further below Ev are charged, but they are neutral under an operation bias and must be excluded in the lifetime prediction. The new technique allows quantitative determination of the correct level of as-grown hole trapping to be included in the lifetime prediction. A main advantage of the proposed technique is that the contribution of as-grown hole traps is experimentally measured, avoiding the use of trap-filling models and the associated fitting parameters. The successful separation of as-grown hole trapping from the total degradation allows the extraction of generated defects and restores the power-law kinetics. Based on this new lifetime prediction technique, it is concluded that the maximum operation voltage for a 10 years lifetime is substantially overestimated by the conventional prediction technique. This new lifetime prediction technique has been accepted for presentation at the 2013 International Electron Devices Meeting (IEDM)

Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works