DIMENSION REDUCTION FOR POWER SYSTEM MODELING USING PCA METHODS CONSIDERING INCOMPLETE DATA READINGS

Principal Component Analysis (PCA) is a popular method for dimension reduction that can be used in many fields including data compression, image processing, exploratory data analysis, etc. However, traditional PCA method has several drawbacks, since the traditional PCA method is not efficient for dealing with high dimensional data and cannot be effectively applied to compute accurate enough principal components when handling relatively large portion of missing data. In this report, we propose to use EM-PCA method for dimension reduction of power system measurement with missing data, and provide a comparative study of traditional PCA and EM-PCA methods. Our extensive experimental results show that EM-PCA method is more effective and more accurate for dimension reduction of power system measurement data than traditional PCA method when dealing with large portion of missing data set

Уменьшение нагрева радиоэлектронных компонентов численной оптимизацией конструкции

В процессе проектирования конструкции методы оптимизации могут использоваться с целью изучения пространства проектирования, то есть концептуального пространства, охватывающего диапазон значений выходных переменных проектирования. Применение численной оптимизации конструкции по предварительно отобранным входным параметрам позволяет определить их наилучшие значения для уменьшения разогрева электронных компонентов

Learning Approaches to Analog and Mixed Signal Verification and Analysis

The increased integration and interaction of analog and digital components within a system has amplified the need for a fast, automated, combined analog, and digital verification methodology. There are many automated characterization, test, and verification methods used in practice for digital circuits, but analog and mixed signal circuits suffer from long simulation times brought on by transistor-level analysis. Due to the substantial amount of simulations required to properly characterize and verify an analog circuit, many undetected issues manifest themselves in the manufactured chips. Creating behavioral models, a circuit abstraction of analog components assists in reducing simulation time which allows for faster exploration of the design space. Traditionally, creating behavioral models for non-linear circuits is a manual process which relies heavily on design knowledge for proper parameter extraction and circuit abstraction. Manual modeling requires a high level of circuit knowledge and often fails to capture critical effects stemming from block interactions and second order device effects. For this reason, it is of interest to extract the models directly from the SPICE level descriptions so that these effects and interactions can be properly captured. As the devices are scaled, process variations have a more profound effect on the circuit behaviors and performances. Creating behavior models from the SPICE level descriptions, which include input parameters and a large process variation space, is a non-trivial task. In this dissertation, we focus on addressing various problems related to the design automation of analog and mixed signal circuits. Analog circuits are typically highly specialized and fined tuned to fit the desired specifications for any given system reducing the reusability of circuits from design to design. This hinders the advancement of automating various aspects of analog design, test, and layout. At the core of many automation techniques, simulations, or data collection are required. Unfortunately, for some complex analog circuits, a single simulation may take many days. This prohibits performing any type of behavior characterization or verification of the circuit. This leads us to the first fundamental problem with the automation of analog devices. How can we reduce the simulation cost while maintaining the robustness of transistor level simulations? As analog circuits can vary vastly from one design to the next and are hardly ever comprised of standard library based building blocks, the second fundamental question is how to create automated processes that are general enough to be applied to all or most circuit types? Finally, what circuit characteristics can we utilize to enhance the automation procedures? The objective of this dissertation is to explore these questions and provide suitable evidence that they can be answered. We begin by exploring machine learning techniques to model the design space using minimal simulation effort. Circuit partitioning is employed to reduce the complexity of the machine learning algorithms. Using the same partitioning algorithm we further explore the behavior characterization of analog circuits undergoing process variation. The circuit partitioning is general enough to be used by any CMOS based analog circuit. The ideas and learning gained from behavioral modeling during behavior characterization are used to improve the simulation through event propagation, input space search, complexity and information measurements. The reduction of the input space and behavioral modeling of low complexity, low information primitive elements reduces the simulation time of large analog and mixed signal circuits by 50-75%. The method is extended and applied to assist in analyzing analog circuit layout. All of the proposed methods are implemented on analog circuits ranging from small benchmark circuits to large, highly complex and specialized circuits. The proposed dependency based partitioning of large analog circuits in the time domain allows for fast identification of highly sensitive transistors as well as provides a natural division of circuit components. Modeling analog circuits in the time domain with this partitioning technique and SVM learning algorithms allows for very fast transient behavior predictions, three orders of magnitude faster than traditional simulators, while maintaining 95% accuracy. Analog verification can be explored through a reduction of simulation time by utilizing the partitions, information and complexity measures, and input space reduction. Behavioral models are created using supervised learning techniques for detected primitive elements. We will show the effectiveness of the method on four analog circuits where the simulation time is decreased by 55-75%. Utilizing the reduced simulation method, critical nodes can be found quickly and efficiently. The nodes found using this method match those found by an experienced layout engineer, but are detected automatically given the design and input specifications. The technique is further extended to find the tolerance of transistors to both process variation and power supply fluctuation. This information allows for corrections in layout overdesign or guidance in placing noise reducing components such as guard rings or decoupling capacitors. The proposed approaches significantly reduce the simulation time required to perform the tasks traditionally, maintain high accuracy, and can be automated

Τεχνικές ελέγχου ορθής λειτουργίας και διόρθωσης επιδόσεων τηλεπικοινωνιακών ολοκληρωμένων κυκλωμάτων υψηλών συχνοτήτων

Στη διατριβή αυτή παρουσιάζονται τεχνικές ελέγχου ορθής λειτουργίας και διόρθωσης επιδόσεων κατάλληλες για αναλογικά ολοκληρωμένα κυκλώματα RF. Ειδικότερα, προτείνεται η ενοποίηση των διαδικασιών ελέγχου ορθής λειτουργίας και διόρθωσης των επιδόσεων ενός κυκλώματος με την αξιοποίηση ενός συνόλου βέλτιστα επιλεγμένων παρατηρήσιμων μεγεθών. Η επεξεργασία των μεγεθών αυτών καθιστά δυνατή, αφενός, την ανίχνευση ελαττωμάτων και, αφετέρου, την πρόγνωση των επιδόσεων του κυκλώματος η οποία επιτρέπει την εξέταση της συμμόρφωσής του προς τις προδιαγραφές, καθώς και τη διόρθωση της συμπεριφοράς του. Προκειμένου να αντιμετωπισθεί το πρόβλημα της προσβασιμότητας στα παρατηρήσιμα μεγέθη προτείνεται ενσωματωμένη τεχνική μέτρησής τους, ενώ αναπτύσσεται μέθοδος για την ελαχιστοποίηση της αβεβαιότητας που υπεισέρχεται στο ίδιο το σύστημα μέτρησης. Εφαρμόζονται, επίσης, αλγόριθμοι επιλογής με σκοπό την μείωση του αριθμού των παρατηρήσιμων μεγεθών, μέσω μιας διαδικασίας βελτιστοποίησης η οποία οδηγεί στη μείωση του κόστους ελέγχου ορθής λειτουργίας με τον περιορισμό της πολυπλοκότητας και της χρονικής διάρκειας διεξαγωγής του. Η αποδοτικότητα των προτεινόμενων τεχνικών επιβεβαιώνεται με την εφαρμογή τους σε τυπικό μίκτη RF τεχνολογίας 0.18μm CMOS, από τον οποίο λαμβάνονται αποτελέσματα προσομοιώσεων που αξιολογούνται και συγκρίνονται με αντίστοιχες συμβατικές τεχνικές.Testing and performance calibration techniques suitable for integrated RF circuits are presented in this dissertation. Specifically, a common approach is proposed for the testing and calibration procedures, that exploits a set of optimally selected observables. The processing of these observables enables defect detection, and also the prediction of the circuit’s performance which allows the examination of compliance with the specifications and performance calibration, as well. In order to address the problem of accessibility to test observables, a built-in technique is proposed, while a method to minimize the uncertainty introduced in the measurement system itself is also described. The application of selection algorithms is explored, aiming to reduce the number of test observables through an optimization procedure that leads to test cost savings due to the reduction of the test conduction complexity and time. The efficiency of the proposed techniques is validated by their application to a typical RF mixer designed in a 0.18um CMOS technology. Simulation results are obtained and assessed, while comparison with similar conventional techniques is also provided