Programmed state assignment algorithms for asynchronous sequential machines.

An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous sequential circuit is the internal state assignment. Although systematic methods have been developed to construct minimum-transition-time state assignments, they become long and tedious with hand methods for machines with more than 7 or 8 internal states. To extend the application of these algorithms to larger problems, this paper presents an efficient digital computer program for generating minimum-variable state assignments. An alternate program is also presented which, though shorter, does not guarantee a minimum-variable assignment --Abstract, page ii

Synthesis heuristics for large asynchronous sequential circuits

Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii

Improving Connectionist Energy Minimization

Symmetric networks designed for energy minimization such as Boltzman machines and Hopfield nets are frequently investigated for use in optimization, constraint satisfaction and approximation of NP-hard problems. Nevertheless, finding a global solution (i.e., a global minimum for the energy function) is not guaranteed and even a local solution may take an exponential number of steps. We propose an improvement to the standard local activation function used for such networks. The improved algorithm guarantees that a global minimum is found in linear time for tree-like subnetworks. The algorithm, called activate, is uniform and does not assume that the network is tree-like. It can identify tree-like subnetworks even in cyclic topologies (arbitrary networks) and avoid local minima along these trees. For acyclic networks, the algorithm is guaranteed to converge to a global minimum from any initial state of the system (self-stabilization) and remains correct under various types of schedulers. On the negative side, we show that in the presence of cycles, no uniform algorithm exists that guarantees optimality even under a sequential asynchronous scheduler. An asynchronous scheduler can activate only one unit at a time while a synchronous scheduler can activate any number of units in a single time step. In addition, no uniform algorithm exists to optimize even acyclic networks when the scheduler is synchronous. Finally, we show how the algorithm can be improved using the cycle-cutset scheme. The general algorithm, called activate-with-cutset, improves over activate and has some performance guarantees that are related to the size of the network's cycle-cutset.Comment: See http://www.jair.org/ for any accompanying file

Automation In The Design Of Asynchronous Sequential Circuits

Sequential switching circuits are commonly classified as being either synchronous or asynchronous. Clock pulses synchronize the operations of the synchronous circuit. The operation of an asynchronous circuit is usually assumed to be independent of such clocks. The operating speed of an asynchronous circuit is thus limited only by basic device speed. One disadvantage of asynchronous circuit design has been the complexity of the synthesis procedures for large circuits

Modula-2*: An extension of Modula-2 for highly parallel programs

Parallel programs should be machine-independent, i.e., independent of properties that are likely to differ from one parallel computer to the next. Extensions are described of Modula-2 for writing highly parallel, portable programs meeting these requirements. The extensions are: synchronous and asynchronous forms of forall statement; and control of the allocation of data to processors. Sample programs written with the extensions demonstrate the clarity of parallel programs when machine-dependent details are omitted. The principles of efficiently implementing the extensions on SIMD, MIMD, and MSIMD machines are discussed. The extensions are small enough to be integrated easily into other imperative languages

Synthesis of multiple-input change asynchronous finite state machines

Asynchronous finite state machines (AFSMS) have been limited because multiple-input changes have been disallowed. In this paper, we present an architecture and synthesis system to overcome this limitation. The AFSM marks potentially hazardous state transitions, and prevents output during them. A synthesis tool to create the AFS M incorporates novel algorithms to detect the hazardous states

Next-state equation generation for asynchronous sequential circuits - normal mode

This paper describes the known methods of generating next-state equations for asynchronous sequential circuits operating in normal fundamental mode. First, the methods that have been previously developed by other authors are explained and correlated in a simple and uniform language in order that the subtle differences of these approaches can be seen. This review is then followed by a development of a new method for generating minimal next-state equations which has some advantages over the previous methods. From the comparison of the previous known methods, it is noted that any one of these methods may be desirable for certain designs since each has some advantages that the others do not have. However, these methods also have limitations in that some methods can only be used with particular types of assignments. Also, as flow tables become larger the amount of work required to use some of these methods becomes excessive and tedious. The method developed here is a simple and straightforward approach which can be used for any unicode, single transition time assignment and will easily lend itself to computer application. The heart of this method emanates from the role that the Karnaugh map plays in the conventional approach for generating the next-state equations. The main advantage of this method seems to be its capability and proficiency in handling large flow tables --Abstract, pages ii-iii