Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

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Integração de modelos de atraso e consumo de portas lógicas CMOS no ambiente de geração automática SwitchCraft

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Design and analysis of SRAMs for energy harvesting systems

PhD ThesisAt present, the battery is employed as a power source for wide varieties of microelectronic systems ranging from biomedical implants and sensor net-works to portable devices. However, the battery has several limitations and incurs many challenges for the majority of these systems. For instance, the design considerations of implantable devices concern about the battery from two aspects, the toxic materials it contains and its lifetime since replacing the battery means a surgical operation. Another challenge appears in wire-less sensor networks, where hundreds or thousands of nodes are scattered around the monitored environment and the battery of each node should be maintained and replaced regularly, nonetheless, the batteries in these nodes do not all run out at the same time. Since the introduction of portable systems, the area of low power designs has witnessed extensive research, driven by the industrial needs, towards the aim of extending the lives of batteries. Coincidentally, the continuing innovations in the field of micro-generators made their outputs in the same range of several portable applications. This overlap creates a clear oppor-tunity to develop new generations of electronic systems that can be powered, or at least augmented, by energy harvesters. Such self-powered systems benefit applications where maintaining and replacing batteries are impossi-ble, inconvenient, costly, or hazardous, in addition to decreasing the adverse effects the battery has on the environment. The main goal of this research study is to investigate energy harvesting aware design techniques for computational logic in order to enable the capa- II bility of working under non-deterministic energy sources. As a case study, the research concentrates on a vital part of all computational loads, SRAM, which occupies more than 90% of the chip area according to the ITRS re-ports. Essentially, this research conducted experiments to find out the design met-ric of an SRAM that is the most vulnerable to unpredictable energy sources, which has been confirmed to be the timing. Accordingly, the study proposed a truly self-timed SRAM that is realized based on complete handshaking protocols in the 6T bit-cell regulated by a fully Speed Independent (SI) tim-ing circuitry. The study proved the functionality of the proposed design in real silicon. Finally, the project enhanced other performance metrics of the self-timed SRAM concentrating on the bit-line length and the minimum operational voltage by employing several additional design techniques.Umm Al-Qura University, the Ministry of Higher Education in the Kingdom of Saudi Arabia, and the Saudi Cultural Burea

Modeling and Fabrication of Low Power Devices and Circuits Using Low-Dimensional Materials

University of Minnesota Ph.D. dissertation.July 2016. Major: Electrical Engineering. Advisor: Steven Koester. 1 computer file (PDF); x, 112 pages.As silicon approaches its ultimate scaling limit as a channel material for conventional semiconductor devices, alternate mechanisms and materials are emerging rapidly to replace or complement conventional silicon based devices. Attractive semiconducting properties such as high mobility, excellent interface quality, and better scalability are the properties desired for materials to be explored for electronic and photonic device applications. Hybrid III-V semiconductor based tunneling field effect transistors (TFETs) can provide a strong alternative due to their attractive properties such as subthreshold slopes less than 60 mV/decade, which can lead to aggressive power supply scaling. Here, InAs-SiGe-Si based TFETs are studied in detail. Simulations predict that subthreshold slopes as low as 18 mV/decade and on currents as high as 50 µA/µm can be achieved using such a device. However, the simulations also show that the device performance is limited by (1) the low density of states in the source which induces a trade-off between the source doping and the subthreshold slope, limiting power supply scaling, and (2) direct source-to-drain tunneling which limits gate length scaling. Another approach to explore low power alternatives to conventional semiconductor device can be to use emerging two-dimensional (2D) materials. In particular, the transition metal dichalcogenides (TMDs) are promising material group that, like graphene, these material exhibit 2D nature, but unlike graphene, have a finite band gap. In this work, the off-state characteristics are modelled for MoS2 MOSFETs (metal–oxide–semiconductor field-effect transistors), and their circuit performance is predicted. MoS2 Due to its higher effective masses and large band gap compared to silicon it is shown that MoS2 MOSFETs are well suited for dynamic memory applications. Two of such circuits, one transistor one capacitor (1TIC) and two transistor (2T) dynamic memory cells have been fabricated for the first time. Retention times as high as 0.25 second and 1.3 second for the 1T1C and 2T cell, respectively, are demonstrated. Moreover, ultra-low leakage currents less than femto-ampere per micron are extracted based on the retention time measurements. These results establish the potential of 2D MoS2 as an attractive material for low power device and circuit applications

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications

Biblioteca de BDDs baseada em inteiros

Diagramas de decisão binária (BDDs) são um tipo de estrutura de dados muito usada no projeto de circuitos integrados digitais. Este trabalho apresenta uma contribuição para a obtenção de estruturas de dados mais eficientes para BDDs através da proposta de uma chave única baseada em um só inteiro. Para operações lógicas de oito entradas ou mais, esta implementação foi de duas a treze vezes mais rápida do que uma implementação de referência onde a chave única é baseada em cadeias de caracteres. Para circuitos aritméticos cujas entradas possuem três bits ou mais, o resultado obtido foi um ganho de velocidade de 2,5 à 9,4 vezes.BDDs are a type of data structure widely used in the design of digital integrated circuits. This work presents a contribution to obtain more efficient BDD data structures through using a unique key based on a single integer. For logic operations of eight inputs or more, this implementation was two to thirteen times faster compared to a reference implementation where the unique key is based in a string of characters. For arithmetic circuits of two three or more bits inputs, the result obtained was a 2.5 to 9.4 times gain in speed

Performance-Based Optical Proximity Correction

Ph.DDOCTOR OF PHILOSOPH

Characterisation of Novel Resistive Switching Memory Devices

Resistive random access memory (RRAM) is widely considered as a disruptive technology that will revolutionize not only non-volatile data storage, but also potentially digital logic and neuromorphic computing. The resistive switching mechanism is generally conceived as the rupture/restoration of defect-formed conductive filament (CF) or defect profile modulation, for filamentary and non-filamentary devices respectively. However, details of the underlying microscopic behaviour of the resistive switching in RRAM are still largely missing. In this thesis, a defect probing technique based on the random telegraph noise (RTN) is developed for both filamentary and non-filamentary devices, which can reveal the resistive switching mechanism at defect level and can also be used to analyse the device performance issues. HfO2 is one of the most matured metal-oxide materials in semiconductor industry and HfO2 RRAM shows promising potential in practical application. An RTN-based defect extraction technique is developed for the HfO2 devices to detect individual defect movement and provide statistical information of CF modification during normal operations. A critical filament region (CFR) is observed and further verified by defect movement tracking. Both defect movements and CFR modification are correlated with operation conditions, endurance failure and recovery. Non-filamentary devices have areal switching characteristics, and are promising in overcoming the drawbacks of filamentary devices that mainly come from the stochastic nature of the CF. a-VMCO is an outstanding non-filamentary device with a set of unique characteristics, but its resistive switching mechanism has not been clearly understood yet. By utilizing the RTN-based defect profiling technique, defect profile modulation in the switching layer is identified and correlated with digital and analogue switching behaviours, for the first time. State instability is analysed and a stable resistance window of 10 for >106 cycles is restored through combining optimizations of device structure and operation conditions, paving the way for its practical application. TaOx-based RRAM has shown fast switching in the sub-nanosecond regime, good CMOS compatibility and record endurance of more than 1012 cycles. Several inconsistent models have been proposed for the Ta2O5/TaOx bilayered structure, and it is difficult to quantify and optimize the performance, largely due to the lack of microscopic description of resistive switching based on experimental results. An indepth analysis of the TiN/Ta2O5/TaOx/TiN structured RRAM is carried out with the RTN-based defect probing technique, for both bipolar and unipolar switching modes. Significant differences in defect profile have been observed and explanations have been provided

Attacking and Defending Emerging Computer Systems Using The Memory Remanence Effect

In computer systems, manufacturing variances and hardware effects are typically abstracted away by the software layer. This dissertation explores how these effects, specifically memory remanence, can be used both as an attack vector and a tool to defend emerging computing systems. To achieve this, we show how time-keeping, anonymity, and authenticity can be affected by memory remanence. In terms of attacks, we explore the deanonymizing effect of approximate computing in the context of approximate memory in Probable Cause. We show how data passing through an approximate memory is watermarked with a device specific tag that points the attacker back to the device. In terms of defenses, we first present TARDIS: an approach to provide a notion of time for transiently powered embedded devices without requiring any hardware modification using remanence effect of SRAM. TARDIS allows these devices to keep a coarse-grained notion of time without the need for a running clock. Second, we propose data retention voltage of memory cells as a new type of physical unclonable function that allows for low-cost authentication and counterfeit resistance in computer systems.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136985/1/rahmati_1.pd