Pulsed digital oscillators

The objective of this paper is to collect the main latest results on pulsed digital oscillators. Rigorous and experimental results are presented that show what kind of sequences are at their output, the relation between these sequences and those of first-order sigma-delta modulators and how is their performance in practical applications. A new variation of the standard topology of PDOs, on which the feedback variable is not position but the velocity of the resonator, is also presented. The first preliminary results obtained with a PDO working with a MEMS cantilever for chemical sensing are presented, which show that it is possible to infer the oscillation frequency directly from the bitstream at the output of the oscillator. Finally, the dependence of the oscillation frequency as a function of the initial conditions of the resonator are also analyzed with simulations.Peer ReviewedPostprint (published version

Finite-power spectral analytic framework for quantized sampled signals

Publication in the conference proceedings of SampTA, Bremen, Germany, 201

Ergodic dynamics in sigma–delta quantization: tiling invariant sets and spectral analysis of error

AbstractThis paper has two themes that are intertwined. The first is the dynamics of certain piecewise affine maps on Rm that arise from a class of analog-to-digital conversion methods called ΣΔ (sigma–delta) quantization. The second is the analysis of reconstruction error associated with each such method.ΣΔ quantization generates approximate representations of functions by sequences that lie in a restricted set of discrete values. These are special sequences in that their local averages track the function values closely, thus enabling simple convolutional reconstruction. In this paper, we are concerned with the approximation of constant functions only, a basic case that presents surprisingly complex behavior. An mth order ΣΔ scheme with input x can be translated into a dynamical system that produces a discrete-valued sequence (in particular, a 0–1 sequence) q as its output. When the schemes are stable, we show that the underlying piecewise affine maps possess invariant sets that tile Rm up to a finite multiplicity. When this multiplicity is one (the single-tile case), the dynamics within the tile is isomorphic to that of a generalized skew translation on Tm.The value of x can be approximated using any consecutive M elements in q with increasing accuracy in M. We show that the asymptotical behavior of reconstruction error depends on the regularity of the invariant sets, the order m, and some arithmetic properties of x. We determine the behavior in a number of cases of practical interest and provide good upper bounds in some other cases when exact analysis is not yet available

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe