Mechanics of Non Planar Interfaces in Flip-Chip Interconnects

With the continued proliferation of low cost, portable consumer electronic products with greater functionality, there is increasing demand for electronic packaging that is smaller, lighter and less expensive. Flip chip is an essential enabling technology for these products. The electrical connection between the chip I/O and substrate is achieved using conductive materials, such as solder, conductive epoxy, metallurgy bump (e.g., gold) and anisotropic conductive adhesives. The interconnect regions of flip-chip packages consists of highly dissimilar materials to meet their functional requirements. The mismatches in properties, contact morphology and crystal orientation at those material interfaces make them vulnerable to failure through delamination and crack growth under various loading patterns. This study encompasses contact between deformable bodies, bonding at the asperities and fracture properties at interfaces formed by the interconnects of flip-chip packages. This is achieved through experimentation and modeling at different length scales, to be able to capture the detailed microstructural features and contact mechanics at interfaces typically found in electronic systems

Lead-Free Solder Pull-Off Stress Comparison of a Novel Bump Pull Method with Conventional Hot/Cold Bump Pull Methods

A novel method for directly testing the adhesion strength of three lead-free solders was developed and compared with conventional methods. The Isotraction Bump Pull method utilizes a combination of favorable qualities of the Cold and Hot Bump Pull tests. Solder bumps were generated onto copper printed circuit board substrates using an in-house-fabricated solder bump-on-demand generator. The method uses polymer epoxy to encapsulate solder bumps under uniform tractions, and tested under tension for pull-off stresses. Maximum pull-off stresses for the novel method are: 18MPa (Sn-3.5Ag), 16MPa (SAC 305) and 22MPa (Sn-0.7Cu) and fall at the low end in the literature comparisons. It is suggested that since the copper substrates used in the current work were untreated, that the lower pull-off stress values resulted. Energy Dispersive X-Ray Spectrometry of the newly created faces after fracture shows that brittle fracture of the Intermetallic Compound layer was the mode of failure

MICROSTRUCTURAL CHARACTERIZATION AND THERMAL CYCLING RELIABILITY OF SOLDERS UNDER ISOTHERMAL AGING AND ELECTRICAL CURRENT

Solder joints on printed circuit boards provide electrical and mechanical connections between electronic devices and metallized patterns on boards. These solder joints are often the cause of failure in electronic packages. Solders age under storage and operational life conditions, which can include temperature, mechanical loads, and electrical current. Aging occurring at a constant temperature is called isothermal aging. Isothermal aging leads to coarsening of the bulk microstructure and increased interfacial intermetallic compounds at the solder-pad interface. The coarsening of the solder bulk degrades the creep properties of solders, whereas the voiding and brittleness of interfacial intermetallic compounds leads to mechanical weakness of the solder joint. Industry guidelines on solder interconnect reliability test methods recommend preconditioning the solder assemblies by isothermal aging before conducting reliability tests. The guidelines assume that isothermal aging simulates a "reasonable use period," but do not relate the isothermal aging levels with specific use conditions. Studies on the effect of isothermal aging on the thermal cycling reliability of tin-lead and tin-silver-copper solders are limited in scope, and results have been contradictory. The effect of electrical current on solder joints has been has mostly focused on current densities above 104A/cm2 with high ambient temperature (≥100oC), where electromigration, thermomigration, and Joule heating are the dominant failure mechanisms. The effect of current density below 104A/cm2 on temperature cycling fatigue of solders has not been established. This research provides the relation between isothermal aging and the thermal cycling reliability of select Sn-based solders. The Sn-based solders with 3%, 1%, and 0% silver content that have replaced tin-lead are studied and compared against tin-lead solder. The activation energy and growth exponents of the Arrhenius model for the intermetallic growth in the solders are provided. An aging metric to quantify the aging of solder joints, in terms of phase size in the solder bulk and interfacial intermetallic compound thickness at the solder-pad interface, is established. Based on the findings of thermal cycling tests on aged solder assemblies, recommendations are made for isothermal aging of solders before thermal cycling tests. Additionally, the effect of active electrical current at 103 A/cm2 on thermal cycling reliability is reported

TEMPERATURE CYCLING RELIABILITY OF REBALLED AND REWORKED BALL GRID ARRAY PACKAGES IN SNPB AND SAC ASSEMBLY

In recent years, many countries banned the use of lead in select high volume electronic equipment. However, exemptions from lead-free legislation have been granted for certain products, especially those intended for high-reliability applications. Manufacturers with exemption are facing dwindling supply of lead-based components for their products. This change has left many high-reliability electronic equipment manufacturers with the choices of, mixing lead-free components in tin-lead assembly process, converting products to lead-free, or reprocessing lead-free components to comply with the tin-lead assembly process. Reballing has been used for component reclamation, but right now it offers a way to reprocess the ball grid array packages. The reliability of reballed BGA assembly needs to be determined before the implementation. Mixing lead-free ball grid array packages with eutectic tin-lead solder paste bring new challenges to the current electronic industry. The mixed assemblies with long-term reliability need to be investigated. Although rework has been implemented for decades, the impact of multiple rework process on the reliability of lead-free and mixed assemblies is still unknown. Lead-free ball grid array packages with Sn3.0Ag0.5Cu solder balls were subjected to the reballing process. Ball shear test and cold bump pull test were used to investigate the solder ball attachment strength of the reballed BGAs. Temperature cycling test was used to evaluate the temperature cycling reliability of reballed tin-lead, lead-free and mixed assemblies. The solder ball strength and the temperature cycling reliability of reballed components were independent of the reballing method. The temperature cycling reliability of mixed assemblies was equivalent to that of lead-free assemblies. Microstructure differences in lead-free, mixed and reballed tin-lead assemblies were investigated to explain the temperature cycling reliability results. Lead-free and mixed assemblies were subjected to the rework process. Temperature cycling test was used to evaluate the temperature cycling reliability of reworked assemblies. Cu over-consumption, Cu pad dissolution and thick interfacial intermetallic layer were found in the reworked assemblies. Microstructural investigation and geometry analysis were used to analyze the temperature cycling reliability degradation in the reworked assemblies after multiples rework processes

An Investigation of Reliability of High Density Electronic Package-to-Board Interconnections from the Perspective of Solder Joint Metallurgy

The integration and miniaturization trend of the electronic packaging leads to much finer pitch of the device and package lead terminations. Several reliability concerns and issues that were previously not encountered are now surfacing. The objective of this thesis work is to investigate the reliability of the package-to-board interconnection from the perspective of solder joint metallurgy. It was carried out with several advanced packages such as CSP, WLCSP and leadless ceramic packages on organic laminate PWBs using tin-silver-copper based interconnection materials. The assemblies were subjected to several loading conditions and levels such as thermal, mechanical, and environmental stresses. As expected, the board level reliability (BLR) of electronic assemblies strongly depended on microstructure and morphology of the solder joints. Dispersion strengthening effect of the intermetallic compounds (IMCs), coarsening of the IMC particles, strain rate hardening, solder fatigue, and recrystallization of Sn grains in the highly stressed areas were observed. These were found to directly impact Pb-free solder joint reliability. Appropriate thermal aging can improve joint reliability up to 50% due to coarsening of the IMC particles. In addition, other factors such as dissolution of metals, interfacial reactions, IMC spalling, and cross interaction of surface materials on the two sides of the joints were also observed and discussed. The effects can be expressed as a series of interactive relationships: materials (pad surface materials and solder alloy composition) and/or soldering process lead to microstructure change in bulk solder and/or at interface, which in turn leads to joint reliability variation

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Harsh-Environment Packaging for Downhole Gas and Oil Exploration

This research into new packaging materials and methods for elevated temperatures and harsh environment electronics focused on gaining a basic understanding of current state-of-the-art in electronics packaging used in industry today, formulating the thermal-mechanical models of the material interactions and developing test structures to confirm these models. Discussions were initiated with the major General Electric (GE) businesses that currently sell into markets requiring high temperature electronics and packaging. They related the major modes of failure they encounter routinely and the hurdles needed to be overcome in order to improve the temperature specifications of these products. We consulted with our GE business partners about the reliability specifications and investigated specifications and guidelines that from IPC and the SAE body that is currently developing guidelines for electronics package reliability. Following this, a risk analysis was conducted for the program to identify the critical risks which need to be mitigated in order to demonstrate a flex-based packaging approach under these conditions. This process identified metal/polyimide adhesion, via reliability for flex substrates and high temperature interconnect as important technical areas for reliability improvement

Achieving Improved Reliability with Failure Analysis

Reliability is the ability of a product to properly function, within specified performance limits, for a specified period of time, under the life cycle application conditions. Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and sophisticated supply chains, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes and, customer dissatisfaction due to recurring failures. The PDC (Professional Development Course) starts with an introduction to reliability concepts, physics of failure and an overview of failure mechanisms that affect PCBs (Printed Circuit Boards), PCBAs (Printed Circuit Board Assembly) and components. The PDC then dives into root cause hypothesizing techniques (Pareto, FMEA (Failure Modes and Effects Analysis), fishbone (Cause-And-Effect Diagram), FTA (Fault Tree Analysis)), non-destructive and destructive analysis and, materials characterization will be discussed. Numerous failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies. What Attendees will Learn: Topics include: Overview of Reliability Concepts Failure mechanisms of electronic products Root cause analysis Failure analysis techniques -Non-destructive techniques (optical, CSAM (Confocal Scanning Electron Microscopy) etc.) -Destructive analysis (DPA (Destructive Physical Analysis), Decap (Decapsulation), FIB (Focused Ion Beam) etc.) -Materials characterization (XRF (X-Ray Fluorescence) , EDS (Error Detection Sequential), TMA/DSC (Thermal Mechanical Analysis/Differential Scanning Calorimetry) etc.