Speed Error Mitigation for a DSP-Based Resolver-to-Digital Converter Using Auto-Tuning Filters

Modern resolver-to-digital converters (RDC) are typically implemented using DSP techniques to reduce hardware footprint and enhanced system accuracy. However, in such implementations, both resolver sensor and ADC channel unbalances introduce significant errors particularly in the speed output of the tracking loop. The frequency spectrum of the output error is variable depending on the resolver mechanical velocity. This paper presents the design of an auto-tuning output filter based on the interpolation of pre-computed filters for a DSP-based RDC with a type-II tracking loop. A fourth-order peak and a second-order high pass filter are designed and tested for an experimental RDC. The experimental results demonstrate significant reduction of the peak-to-peak error in the estimated speed

A resolver-to-digital conversion method based on third-order rational fraction polynomial approximation for PMSM control

—In this paper, a cost-effective and highly accurate resolver-to-digital conversion (RDC) method is presented. The core of the idea is to apply a third-order rational fraction polynomial approximation (TRFPA) for the conversion of sinusoidal signals into the pseudo linear signals, which are extended to the range 0-360° in four quadrants. Then, the polynomial least squares method (PLSM) is used to achieve compensation to acquire the final angles. The presented method shows better performance in terms of accuracy and rapidity compared with the commercial available techniques in simulation results. This paper describes the implementation details of the proposed method and the way to incorporate it in digital signal processor (DSP) based permanent magnet synchronous motor (PMSM) drive system. Experimental tests under different conditions are carried out to verify the effectiveness for the proposed method. The obtained maximum error is about 0.0014° over 0-360° , which can usually be ignored in most industrial applications. Index Terms—Arc tangent function, Analog processing circuits, Pseudo linear signals, Resolver-to-digital conversion (RDC), Third-order rational fraction polynomial approximation (TRFPA)

A resolver-to-digital conversion method based on third-order rational fraction polynomial approximation for PMSM control

In this paper, a cost-effective and highly accurate resolver-to-digital conversion (RDC) method is presented. The core of the idea is to apply a third-order rational fraction polynomial approximation (TRFPA) for the conversion of sinusoidal signals into the pseudo linear signals, which are extended to the range 0-360° in four quadrants. Then, the polynomial least squares method (PLSM) is used to achieve compensation to acquire the final angles. The presented method shows better performance in terms of accuracy and rapidity compared with the commercial available techniques in simulation results. This paper describes the implementation details of the proposed method and the way to incorporate it in digital signal processor (DSP) based permanent magnet synchronous motor (PMSM) drive system. Experimental tests under different conditions are carried out to verify the effectiveness for the proposed method. The obtained maximum error is about 0.0014° over 0-360°, which can usually be ignored in most industrial application

ANALYSIS AND SYNTHESIS OF PRECISION RESOLVER SYSTEM

Ph.DDOCTOR OF PHILOSOPH