Korkeataajuisten 65nm CMOS LC oscillaattoreiden käyttö kelojen hyvyysarvon todentamisessa

High quality factor inductors are essential for the design of low phase noise LC oscillators which play an important role in the transceivers of wireless communication devices. The reception capabilities of a radio frequency receiver are to great extent defined by the phase noise performance of the local oscillator. It is therefore important for modern single chip fully integrated transceiver design that high quality inductors are available and well modeled. In this work we investigate the possibility of evaluating the quality factor of an inductor by the phase noise it generates when used in a reference oscillator. A differential CMOS LC oscillator is designed for inductor test benching. The designed oscillator is fabricated on a 65nm CMOS process with two different inductor designs with simulated quality factors of 7.4 and 10.2. The overall combined silicon area of the two oscillators including inductors and probing pads is 680μm by 510μm. The oscillation frequencies are dictated by the designed inductors and were measured 3.04GHz and 4.56GHz. The oscillators achieve a phase noise of -125dBc/Hz and -124dBc/Hz at 1MHz offset with 14mW and 16mW power dissipation respectively. An oscillator phase noise model is fitted to the measured phase noise data of both oscillators and the model parameters are compared. The received quality factors for the designed inductors are 8.2 ± 0.8 and 10.8 ± 0.6 respectively. It was found that the measured phase noise is in good agreement with the results predicted by the model and the relative quality factor can, with certain limitations, be estimated through relative phase noise measurements

Design and implementation of fully integrated low-voltage low-noise CMOS VCO.

Yip Kim-fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 95-100).Abstracts in English and Chinese.Abstract --- p.IAcknowledgement --- p.IIITable of Contents --- p.IVChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Objective --- p.6Chapter Chapter 2 --- Theory of Oscillators --- p.7Chapter 2.1 --- Oscillator Design --- p.7Chapter 2.1.1 --- Loop-Gain Method --- p.7Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10Chapter Chapter 3 --- Noise Analysis --- p.15Chapter 3.1 --- Origin of Noise Sources --- p.16Chapter 3.1.1 --- Flicker Noise --- p.16Chapter 3.1.2 --- Thermal Noise --- p.17Chapter 3.1.3 --- Noise Model of Varactor --- p.18Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19Chapter 3.2 --- Derivation of Resonator --- p.19Chapter 3.3 --- Phase Noise Model --- p.22Chapter 3.3.1 --- Leeson's Model --- p.23Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42Chapter 4.1 --- Device Modeling --- p.42Chapter 4.1.1 --- FET model --- p.42Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46Chapter 4.1.3 --- Planar Inductor --- p.48Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50Chapter 4.1.5 --- Inductor Layout Consideration --- p.54Chapter 4.1.6 --- CMOS RF Varactor --- p.55Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62Chapter 5.1.4 --- Output buffer --- p.63Chapter 5.1.5 --- Biasing Circuitry --- p.64Chapter 5.2 --- Spiral Inductor Design --- p.65Chapter 5.3 --- Determination of W/L ratio of FET --- p.67Chapter 5.4 --- Varactor Design --- p.68Chapter 5.5 --- Layout (Cadence) --- p.69Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74Chapter Chapter 6 --- Experimental Results and Discussion --- p.76Chapter 6.1 --- Measurement Setup --- p.76Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81Chapter 6.2.1 --- Output Spectrum --- p.81Chapter 6.2.2 --- Phase Noise Performance --- p.82Chapter 6.2.3 --- Tuning Characteristic --- p.83Chapter 6.2.4 --- Microphotograph --- p.84Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85Chapter 6.3.1 --- Output Spectrum --- p.85Chapter 6.3.2 --- Phase Noise Performance --- p.86Chapter 6.3.3 --- Tuning Characteristic --- p.87Chapter 6.3.4 --- Microphotograph --- p.88Chapter 6.4 --- Comparison of Measured Results --- p.89Chapter 6.4.1 --- Phase Noise Performance --- p.89Chapter 6.4.2 --- Tuning Characteristic --- p.90Chapter Chapter 7 --- Conclusion and Future Work --- p.93Chapter 7.1 --- Conclusion --- p.93Chapter 7.2 --- Future Work --- p.94References --- p.95Author's Publication --- p.100Appendix A --- p.101Appendix B --- p.104Appendix C --- p.10

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation

Analysis of the high frequency substrate noise effects on LC-VCOs

La integració de transceptors per comunicacions de radiofreqüència en CMOS pot quedar seriosament limitada per la interacció entre els seus blocs, arribant a desaconsellar la utilització de un únic dau de silici. El soroll d’alta freqüència generat per certs blocs, com l’amplificador de potencia, pot viatjar pel substrat i amenaçar el correcte funcionament de l’oscil·lador local. Trobem tres raons importants que mostren aquest risc d’interacció entre blocs i que justifiquen la necessitat d’un estudi profund per minimitzar-lo. Les característiques del substrat fan que el soroll d’alta freqüència es propagui m’és fàcilment que el de baixa freqüència. Per altra banda, les estructures de protecció perden eficiència a mesura que la freqüència augmenta. Finalment, el soroll d’alta freqüència que arriba a l’oscil·lador degrada al seu correcte comportament. El propòsit d’aquesta tesis és analitzar en profunditat la interacció entre el soroll d’alta freqüència que es propaga pel substrat i l’oscil·lador amb l’objectiu de poder predir, mitjançant un model, l’efecte que aquest soroll pot tenir sobre el correcte funcionament de l’oscil·lador. Es volen proporcionar diverses guies i normes a seguir que permeti als dissenyadors augmentar la robustesa dels oscil·ladors al soroll d’alta freqüència que viatja pel substrat. La investigació de l’efecte del soroll de substrat en oscil·ladors s’ha iniciat des d’un punt de vista empíric, per una banda, analitzant la propagació de senyals a través del substrat i avaluant l’eficiència d’estructures per bloquejar aquesta propagació, i per altra, determinant l’efecte d’un to present en el substrat en un oscil·lador. Aquesta investigació ha mostrat que la injecció d’un to d’alta freqüència en el substrat es pot propagar fins arribar a l’oscil·lador i que, a causa del ’pulling’ de freqüència, pot modular en freqüència la sortida de l’oscil·lador. A partir dels resultats de l’anàlisi empíric s’ha aportat un model matemàtic que permet predir l’efecte del soroll en l’oscil·lador. Aquest model té el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem. el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem.The integration of transceivers for RF communication in CMOS can be seriously limited by the interaction between their blocks, even advising against using a single silicon die. The high frequency noise generated by some of the blocks, like the power amplifier, can travel through the substrate, reaching the local oscillator and threatening its correct performance. Three important reasons can be stated that show the risk of the single die integration. Noise propagation is easier the higher the frequency. Moreover, the protection structures lose efficiency as the noise frequency increases. Finally, the high frequency noise that reaches the local oscillator degrades its performance. The purpose of this thesis is to deeply analyze the interaction between the high frequency substrate noise and the oscillator with the objective of being able to predict, thanks to a model, the effect that this noise may have over the correct behavior of the oscillator. We want to provide some guidelines to the designers to allow them to increase the robustness of the oscillator to high frequency substrate noise. The investigation of the effect of the high frequency substrate noise on oscillators has started from an empirical point of view, on one hand, analyzing the noise propagation through the substrate and evaluating the efficiency of some structures to block this propagation, and on the other hand, determining the effect on an oscillator of a high frequency noise tone present in the substrate. This investigation has shown that the injection of a high frequency tone in the substrate can reach the oscillator and, due to a frequency pulling effect, it can modulate in frequency the output of the oscillator. Based on the results obtained during the empirical analysis, a mathematical model to predict the effect of the substrate noise on the oscillator has been provided. The main advantage of this model is the fact that it is based on physical parameters of the oscillator and of the noise, allowing to determine the measures that a designer can take to increase the robustness of the oscillator as well as the consequences (trade-offs) that these measures have over its global performance. This model has been compared against both, simulations and real measurements, showing a very high accuracy to predict the effect of the high frequency substrate noise. The usefulness of the presented model as a design tool has been demonstrated in two case studies. Firstly, the conclusions obtained from the model have been applied in the design of an ultra low power consumption 2.5 GHz oscillator robust to the high frequency substrate noise with characteristics which make it compatible with the main communication standards in this frequency band. Finally, the model has been used as an analysis tool to evaluate the cause of the differences, in terms of performance degradation due to substrate noise, measured in two 60 GHz oscillators with two different tank inductor shielding strategies, floating and grounded. The model has determined that the robustness differences are caused by the improvement in the tank quality factor and in the oscillation amplitude and no by an increased isolation between the tank and the substrate. The model has shown to be valid and very accurate even in these extreme frequency range.Postprint (published version

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas