Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime

Covid-19 and its impacts on consumer decision-making process

The term "virus" derives from the Latin word for "venom" and refers to a microscopic infectious agent. On the other hand, "corona" is named by its shape to look like a crown ring – the scientists who coined the word coronavirus in 1968 reasoned that the virus they were studying under a microscope resembled a solar corona (Steinmetz, 2020). COVID-19 was introduced when it was first detected in late 2019 and used letters from CO-Rona-VI-rus D-isease (Bhargava, 2020). Corona infections were initially seen as cold in 1965 (Kahn & McIntosh, 2005), which is almost six decades ago. Corona was formerly thought to be a basic, non-fatal virus to human beings until 2002. Before the world witnessed a Severe Acute Respiratory Syndrome Coronavirus (SARS-CoV) outbreak in November 2002, it was assumed that this virus mainly infected animals. However, this was proven incorrect. Ten years after that, a new pathogenic coronavirus known as the Middle East Respiratory Syndrome Coronavirus (MERS-CoV) spread throughout the Middle East and caused a pandemic in several countries (Shereen et a., 2020)

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

In this thesis, we present a fast algorithm to construct a performance driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently several algorithms like Ptree, Stree, Sptree, and graph-RTBW have been published addressing the routing tree construction problem. But all these algorithms are slow and not scalable. Here we present an algorithm which is fast and scalable with problem size. The main idea of algorithm is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features to evaluate a routing tree, the size of stochastic search space is small which can be searched in very less time. The solutions for the components are either pre-generated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since, the solutions of the components can be constructed efficiently, we can construct and evaluate the whole routing tree efficiently for each specification. Experimental results show that, for trees of moderate size, our algorithm is at least several hundred times faster than the recently proposed algorithms, Sptree and graph-RTBW, with not much difference in delay and resource consumption

Buffer insertion in large circuits using look-ahead and back-off techniques

Buffer insertion is an essential technique for reducing interconnect delay in submicron circuits. Though it is a well researched area, there is a need for robust and effective algorithms to perform buffer insertion at the circuit level. This thesis proposes a new buffer insertion algorithm for large circuits. The algorithm finds a buffering solution for the entire circuit such that buffer cost is minimized and the timing requirements of the circuit are satisfied. The algorithm iteratively inserts buffers in the circuit improving the circuit delay step by step. At the core of this algorithm are very simple but extremely effective techniques that constructively guide the search for a good buffering solution. A flexibility to adapt to the user's requirements and the ability to reduce the number of buffers are the strengths of this algorithm. Experimental results on ISCAS85 benchmark circuits show that the proposed algorithm, on average, yields 36% reduction in the number of buffers, and runs three times faster than one of the best known previously researched algorithms

Simultaneous routing and buffer insertion with restrictions on buffer Locations

During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations

Abstract During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay. 1 Introduction With the evolution of VLSI fabrication technology, interconnect delay, especially global interconnect delay, has become the dominant factor in deep sub-micron design. Many techniques are employed to reduce interconnect delay; among them, buffer insertion has been shown to be an effective approach [2]. During routing process, especially that for global nets, there are macro blocks placed within the area. These blocks form useful routing regions because wires are allowed to run over them. But since buffers are implemented by transistors, a buffer "over " a macro block must be actually put into that block. However, it is impossible to insert a buffer into a macro block if it is an IP (Intellectual Property) where internal structure can not be changed, or it is a block such as memory which requires regular layout. Even in the case when that is theoretically possible, since a re-design of the influenced block is needed, it is usually not allowed due to the design flow. Therefore, macro blocks present themselves as routing resources for wires but obstacles for buffers

Circuit delay optimization by buffering the logic gates

Avec la miniaturisation actuelle, les circuits démontrent de plus en plus l'importance des délais d'interconnexion. Afin de réduire ce délai, l'insertion de tampons doit être effectuée durant la synthèse logique et la synthèse physique. Cette activité d'optimisation est souvent basée sur la programmation dynamique. Dans ce mémoire, la technique branch-and-bound est utilisé et le problème pour le cas spécifique d'arbres de tampons équilibrés est résolu, où toutes les charges ont un temps requis et une capacité identique. Une analyse mathématique est faite pour tenir compte d'une variété de questions de conception telles que la topologie, la bibliothèque de tampons et le changement de phase en présence d'inverseur. En combinant la programmation dynamique et les techniques branch-and-bound, une méthode hybride est présentée qui améliore le temps d'exécution tout en conservant une utilisation de mémoire raisonnable. Les concepts mathématiques et algorithmiques fondamentaux utilisés dans ce mémoire peuvent être employés pour généraliser la méthode proposée pour un ensemble de charges avec des capacités et des temps requis différents

Ein leitbahnorientiertes Verfahren für den physikalischen Entwurf integrierter digitaler Schaltungen

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