Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

The design and development of a 64-Bit Linux based single board computer specifically for visible light positioning

Thesis (MEng)--Stellenbosch University, 2022.ENGLISH SUMMARY: The University of Stellenbosch and Katholieke Universiteit Leuven currently utilise freely available single board computers (SBC) for teaching and research purposes, but updates in future hardware iterations may render current software incompatible. A custom SBC is designed specifically for the needs of both institutions. This SBC is based on the NXP i.MX8MQ ARM processor. The processor has 4 high performance ARM Cortex-A53 cores and 1 high efficiency ARM Cortex-M4F core. This work successfully implements the i.MX8MQ processor alongside 2GB of LPDDR4 memory and SD card storage. This SBC has an analogue to digital converter (ADC), 2 46-pin expansion connectors, 100Mbps Ethernet, HDMI, 2 USB 3.0 and a UART-to-USB serial debug port. The power system of this SBC provides 16 voltage rails and is capable of delivering up to 50W . This design is implemented on a 6-layer 86.36mm x 55.88mm printed circuit board (PCB). The PCB has 4mi l/4mi l minimum width and spacing and 0.2mm via holes. The layer stackup of the PCB is custom designed to meet required impedance-, crosstalk- and timing constraints. The stackup has 4 signal layers, 1 power layer and 1 ground layer. The PCB is manufactured and sub-assembled in China and completed at the University of Stellenbosch. Debugging is performed and the design is deemed to function well. A custom Linux image is compiled, loaded and found to function reliably.AFRIKAANSE OPSMMING: Die Universiteit van Stellenbosch en Katholieke Universiteit Leuven gebruik tans kommersiële enkelbordrekenaars vir onderrig- en navorsingsdoeleindes, maar toekomstige opdateering van hardeware kan bestaande sagteware onbruikbaar maak. ’n Doelgemaakte enkelbordrekenaar is spesifiek ontwerp vir die behoeftes van beide instansies. Hierdie enkelbordrekenaar is gebaseer op die NXP i.MX8MQ ARM verwerker. Die verwerker het 4 hoë krag ARM Cortex-A53 kerne en 1 hoë effektiwiteit ARM Cortex-M4F kern. Die navorsingsprojek implementeer die i.MX8MQ verwerker suksesvol tesame met 2GB LPDDR4 geheue en SD kaartberging. Hierdie enkelbordrekenaar het ’n analoog na digitaal omsetter, 2 46-pen uitbreidingsverbindings, 100Mbps Ethernet, HDMI, 2 USB 3.0 en ’n UART-na-USB ontfoutingspoort. Die kragstelsel van hierdie enkelbordrekenaar lewer 16 spanningsvlakke en is in staat om tot en met 50W te verskaf. Die ontwerp is geïmplementeer op ’n 6-laag 86.36mm x 55.88mm etsbord. Die etsbord het 4mi l/4mi l minimum wydte en spasiëring en 0.2mm via gate. Die laagstapel van die etsbord is spesiaal ontwerp om aan die vereiste impedansie-, kruiskoppeling- en tydsbeperkings te voldoen. Die laagstapel het 4 seinlae, 1 kraglaag en 1 grondlaag. Die etsbord is in Sjina vervaardig en gedeeltelik aanmekaar gesit en dan by die Universiteit van Stellenbosch voltooi. Ontfouting is gedoen en daar is gevind dat die ontwerp goed funksioneer. ’n Doelgemaakte Linux bedryfstelsel is gebou, gelaai en gevind om betroubaar werk.Master

Muon (g-2) Technical Design Report

The Muon (g-2) Experiment, E989 at Fermilab, will measure the muon anomalous magnetic moment a factor-of-four more precisely than was done in E821 at the Brookhaven National Laboratory AGS. The E821 result appears to be greater than the Standard-Model prediction by more than three standard deviations. When combined with expected improvement in the Standard-Model hadronic contributions, E989 should be able to determine definitively whether or not the E821 result is evidence for physics beyond the Standard Model. After a review of the physics motivation and the basic technique, which will use the muon storage ring built at BNL and now relocated to Fermilab, the design of the new experiment is presented. This document was created in partial fulfillment of the requirements necessary to obtain DOE CD-2/3 approval