Simulation and optimization of HEMTs

We have developed a simulation system for nanoscale high-electron mobility transistors, in which the self-consistent solution of Poisson and Schr\"odinger equations is obtained with the finite element method. We solve the exact set of nonlinear differential equations to obtain electron wave function, electric potential distribution, electron density, Fermi surface energy and current density distribution in the whole body of the device. For more precision, local dependence of carrier mobility on the electric field distribution is considered. We furthermore compare the simulation to a recent experimental measurement and observe perfect agreement. We also propose a graded channel design to improve the transconductance and thereby the threshold frequency of the device.Comment: 8 pages, 19 figure

When self-consistency makes a difference

Compound semiconductor power RF and microwave device modeling requires, in many cases, the use of selfconsistent electrothermal equivalent circuits. The slow thermal dynamics and the thermal nonlinearity should be accurately included in the model; otherwise, some response features subtly related to the detailed frequency behavior of the slow thermal dynamics would be inaccurately reproduced or completely distorted. In this contribution we show two examples, concerning current collapse in HBTs and modeling of IMPs in GaN HEMTs. Accurate thermal modeling is proved to be be made compatible with circuit-oriented CAD tools through a proper choice of system-level approximations; in the discussion we exploit a Wiener approach, but of course the strategy should be tailored to the specific problem under consideratio

Effective electrothermal analysis of electronic devices and systems with parameterized macromodeling

We propose a parameterized macromodeling methodology to effectively and accurately carry out dynamic electrothermal (ET) simulations of electronic components and systems, while taking into account the influence of key design parameters on the system behavior. In order to improve the accuracy and to reduce the number of computationally expensive thermal simulations needed for the macromodel generation, a decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed. The approach is applied to study the impact of layout variations on the dynamic ET behavior of a state-of-the-art 8-finger AlGaN/GaN high-electron mobility transistor grown on a SiC substrate. The simulation results confirm the high accuracy and computational gain obtained using parameterized macromodels instead of a standard method based on iterative complete numerical analysis

Investigation into intermodulation distortion in HEMTs using a quasi-2-D physical model

The need for both linear and efficient pseudomorphic high electron-mobility transistors (pHEMTs) for modern wireless handsets necessitates a thorough understanding of the origins of intermodulation distortion at the device level. For the first time, the dynamic large-signal internal physical behavior of a pHEMT is examined using a quasi-two-dimensional physical device model. The model accounts fully for device-circuit interaction and is validated experimentally for a two-tone experiment around 5 GHz

Novel TCAD oriented definition of the off-state breakdown voltage in Schottky-gate FETs: a 4H SiC MESFET case study

Physics-based breakdown voltage optimization in Schottky-barrier power RF and microwave field-effect transistors as well as in high-speed power-switching diodes is today an important topic in technology computer-aided design (TCAD). OFF-state breakdown threshold criteria based on the magnitude of the Schottky-barrier leakage current can be directly applied to TCAD; however, the results obtained are not accurate due to the large uncertainty in the Schottky-barrier parameters and models arising above all in advanced wide-gap semiconductors and to the need of performing high-temperature simulations to improve the numerical convergence of the model. In this paper, we suggest a novel OFF-state breakdown criterion, based on monitoring the magnitude (at the drain edge of the gate) of the electric field component parallel to the current density. The new condition is shown to be consistent with more conventional definitions and to exhibit a significantly reduced sensitivity with respect to physical parameter variation

50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT syste

Parameterized thermal macromodeling for fast and effective design of electronic components and systems

We present a parameterized macromodeling approach to perform fast and effective dynamic thermal simulations of electronic components and systems where key design parameters vary. A decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed to improve the accuracy of the model and reduce the number of the computationally costly thermal simulations needed to build the macromodel. The methodology is successfully applied to analyze the impact of layout variations on the dynamic thermal behavior of a state-of-the-art 8-finger AlGaN/GaN HEMT grown on a SiC substrate