A new design methodology for mixed level and mixed signal simulation using PSpice A/D and VHDL

PSpice A/D is a simulation package that is used to analyze and predict the performance of analog and mixed signal circuits. It is very popular especially among Printed Circuit Board (PCB) engineers to verify board level designs. However, PSpice A/D currently lacks the ability to simulate analog components connected to digital circuits that are modeled using Hardware Descriptive Languages (HDLs), such as VHDL and Verilog HDL. Simulation of HDL models in PSpice A/D is necessary to verify mixed signal PCBs where programmable logic devices like Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are connected to discrete analog components. More than 60% of the PCBs that are designed today contain at least one FPGA or CPLD. This thesis investigates the possibility of simulating VHDL models in PSpice A/D. A new design methodology and the necessary tools to achieve this goal are presented. The new design methodology achieves total system verification at PCB level. Total system verification reduces design failures and hence increases reliability. It also allows reducing the overall time to market. A mixed signal design from NASA Goddard Space Flight Center for a brushless three phase motor that runs a space application is implemented by following the proposed design methodology

Enhanced earthing performance by improved design and grounding material properties

An enhance ground electrode (E.G.E.) is a portable grounding system that acts as an additional grounding system, designed for zero potential reference points. The E.G.E could eliminate the increasing of resistance in grounding conductor as it placed next to the electrical equipment, hence the grounding conductor is shortened. A prototype of E.G.E was developed in size measuring 19.5 em x 19.5 em x 11.5 em and filled with selected grounding material, attached with a grounding electrode. Meanwhile, the grounding electrode was reviewed in terms of thermal conductivity electrode material, variation of soil resistivity with the electrode's depth, and effect on the number of grounding rods to ground resistance. The design ofthe electrode was selected based on heat dispersion that was simulated using the Finite Element Method (FEM) package. The four selected grounding materials chosen based on its resistivity value and physical composition which is; kaolin, sand, bauxite and coal. These materials were investigated using the morphology test, element composition test and correlation between water content and material resistivity test. Fabricated E.G.E was tested under lightning flashover conditions in a HV laboratory using an impulse test generator in order to validate its electrical performance and prolog life expectancy. Data obtained from laboratory tests indicated that bauxite is the best material for the proposed E.G.E system, compared to other materials by offering the lowest different percentage breakdown voltage comparable to native earth, which is around 1.27%. Besides that, bauxite gets 35% strikes during dry condition and 38% strikes during wet condition among three others material. It is hope this E.G.E sustaining a good performance as a grounding system

Modeling and simulation of a digital control design approach for power supply systems

Electronic designers need to model and simulate system features as close as possible to its effective behaviour. Moreover, today, electronics systems are often composed of mixed analog and digital components. The increasing complexity has led to the use of different simulation softwares, each one specific for a particular level of abstraction: mathematical, circuital, behavioural, etc. In order to simulate the entire system these softwares should work together: co-simulation is necessary for digitally controlled power electronics systems. In this paper, the modeling of a digitally controlled switching power supply system using MATLAB/Simulink, ALDEC Active-HDL and Powersys PSIM is presented. The power converter is modelled in PSIM, the digital control is described in VHDL by using Active-HDL, and the complete system is simulated in MATLAB/Simulink environment. This design approach presents all the advantages of each used software and all its features will be discussed. The comparison between simulation and experimental results of the digitally controlled step-down converter prototype are reported

Behavioural simulation of mixed analogue/digital circuits.

Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits

Modeling and simulation of magnetic components in electric circuits

This thesis demonstrates how by using a variety of model constructions and parameter extraction techniques, a range of magnetic component models can be developed for a wide range of application areas, with different levels of accuracy appropriate for the simulation required. Novel parameter extraction and model optimization methods are developed, including the innovative use of Genetic Algorithms and Metrics, to ensure the accuracy of the material models used. Multiple domain modeling, including the magnetic, thermal and magnetic aspects are applied in integrated simulations to ensure correct and complete dynamic behaviour under a range of environmental conditions. Improvements to the original Jiles-Atherton theory to more accurately model loop closure and dynamic thermal behaviour are proposed, developed and tested against measured results. Magnetic Component modeling techniques are reviewed and applied in practical examples to evaluate the effectiveness of lumped models, 1D and 2D Finite Element Analysis models and coupling Finite Element Analysis with Circuit Simulation. An original approach, linking SPICE with a Finite Element Analysis solver is presented and evaluated. Practical test cases illustrate the effectiveness of the models used in a variety of contexts. A Passive Fault Current Limiter (FCL) was investigated using a saturable inductor with a magnet offset, and the comparison between measured and simulated results allows accurate prediction of the behaviour of the device. A series of broadband hybrid transformers for ADSL were built, tested, modeled and simulated. Results show clearly how the Total Harmonic Distortion (THD), Inter Modulation Distortion (IMD) and Insertion Loss (IL) can be accurately predicted using simulation.A new implementation of ADSL transformers using a planar magnetic structure is presented, with results presented that compare favourably with current wire wound techniques. The inclusion of transformer models in complete ADSL hybrid simulations demonstrate the effectiveness of the models in the context of a complete electrical system in predicting the overall circuit performance

Implementation of a CMOS Wallace-tree Multiplier

© ASEE 2009As slow and expensive operation units, multipliers are often the bottleneck limiting the overall performance of many computational VLSI circuits. Various CMOS multiplier architectures are available, such as the array multiplier, carry-save multiplier, and Wallace-tree multiplier. Wallace-tree multiplier has been a very popular design due to its fast speed, ease for modularization and fabrication. In this paper, the design and simulation of an 8-bit Wallace-tree multiplier with PSPICE is proposed. In order for comparison, an 8-bit CMOS array multiplier is also designed. The worst-case delay of both multiplier architectures are extracted and Wallace-tree multiplier demonstrates significant speed enhancement compared to CMOS array multiplier. Some efforts are made to further improve the performance of Wallace-tree multiplier. The revision in the circuit structure demonstrates effective speed improvement for the Wallace-tree multiplier

Moving Towards Analog Functional Safety

Over the past century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power systems. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The standard ISO 26262 related to functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardizing fault modeling, injection and simulation mainly focused on digital circuits and disregarding analog ones. An initial attempt is being made with the IEEE P2427 standard draft standard that started to give this field a structured and formal organization. In this context, new fault models, injection, and abstraction methodologies for analog circuits are proposed in this thesis to enhance this application field. The faults proposed by the IEEE P2427 standard draft standard are initially evaluated to understand the associated fault behaviors during the simulation. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. These new defects proposed are required because digital stuck-at-fault models where a transistor is frozen in on-state or offstate may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. Then, for validating the proposed defects models, a novel predictive fault grouping based on faulty AC matrices is applied to group faults with equivalent behaviors. The proposed fault grouping method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself to faulty AC simulations. Using AC simulations results in two different methods that allow grouping faults with the same frequency response are presented. The first method is an AC-based grouping method that exploits the potentialities of the S-parameters ports. While the second is a Circle-based grouping based on the circle-fitting method applied to the extracted AC matrices. Finally, an open-source framework is presented for the fault injection and manipulation perspective. This framework relies on the shared semantics for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. As a use case for the proposed framework, a process of analog fault injection is discussed. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. The framework is entirely written in C++, and its APIs are also interfaced with Python. The entire framework is open-source and available on GitHub. The last part of the thesis presents abstraction methodologies that can abstract transistor level models into Verilog-AMS models and Verilog- AMS piecewise and nonlinear models into C++. These abstracted models can be integrated into heterogeneous systems. The purpose of integration is the simulation of heterogeneous components embedded in a Virtual Platforms (VP) needs to be fast and accurate

A complete system for controlling and monitoring the timing of the LHCb experiment

The LHCb experiment at CERN will study the results of the production of B/antiB in the LHC accelerator mesons with the higher precision ever. It is vital that the experiment is able to record sub-detectors signals at the optimal detector efficiency, referring to the right collision occurring in the LHC ring, and that those signals are stable, clean and reliable. The solution is the development of a complete system to centrally time align and at the same time to monitor the timing of the whole experiment. An electronics custom-made acquisition board, called Beam Phase and Intensity Monitor (BPIM), has the main aim to monitor the beam processing a bipolar signal coming from a dedicated Beam Pick-Up detector, sitting along the LHC ring and whose signal is a clear representation of the bunches of protons. The BPIM is then able to integrate the intensity of the beam and at the same time to compare the phase of the bunch signal with the clock coming from the timing distribution system as well as the phase of the orbit signal with the signal generated from the first beam bunch. The principal applications of the BPIM are to determine the position of the orbit signal locally, to monitor bunch-by-bunch the clock phase with respect to the bunch passing through the detector, to have a clear structure of the beam injected, to determine the exact trigger conditions for sampling events in the detector, to determine the exact trigger conditions for significative events of not, checking whether the detector samples a bunch with protons (or lead ions) or an empty bunch, to produce an empty crossing veto for the sampled events whenever a bunch is absent in the expected location, to have a relative measure of the intensities of bunch, to have instantaneaous information about the presence/absence of beam, and, not less important, to search for ghost bunches. The board is paired with the RF2TTC system developed by the LHC group and whose aim is to control, clean, convert and transmit the bunch clock (~40 MHz) and the orbit clock (~11 KHz) to the the whole experiment. A complete user-friendly interface system, developed using the SCADA software PVSS II with the Distributed Information Management (DIM) system as communication protocol, allows to control and monitor real-time the available information

Qucs workbook

This document is intended to be a work book for RF and microwave designers.Our intention is not to provide an RF course, but some touchy RF topics. The goal is to insist on design rules and work flow for RF design using CAD programs. This work flow will be handled through different subjects